dec_counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity dec_counter is
    Port ( en : in STD_LOGIC;
           reset : in STD_LOGIC;
           clk : in STD_LOGIC;
           q : out STD_LOGIC_VECTOR (3 downto 0);
           pulse : out STD_LOGIC);
end dec_counter;

architecture Behavioral of dec_counter is
    signal count_s: std_logic_vector(3 downto 0) := (others => '0');
    signal temp: std_logic;
begin
    cnt: process (clk) is
    begin
        if(clk'event and clk = '1') then
            if(reset = '0') then
                if(en = '1') then
                    if(count_s < conv_std_logic_vector(9, 4)) then
                        count_s <= count_s + 1;
                        temp <= '0';
                    else
                        count_s <= (others => '0');
                        temp <= '1';
                    end if;
                end if;
             else
                count_s <= (others => '0');
             end if;
        end if;
    end process;

    q <= count_s;
    pulse <= temp;

end Behavioral;