code_lock_simple_tester

------ code_lock_simple_tester ------
library ieee;
use ieee.std_logic_1164.all;

entity code_lock_simple_tester is
port(
    CLOCK_50    : in std_logic;
    KEY         : in std_logic_vector(1 downto 0);
    SW          : in std_logic_vector(3 downto 0);
    LEDR0       : out std_logic);
end code_lock_simple_tester;


architecture structural of code_lock_simple_tester is
begin

I1: entity work.code_lock_simple
     port map(
     clk    => CLOCK_50,
     reset  => KEY(1),
     code   => SW,
     enter  => KEY(0),
     lock   => LEDR0);

end structural;