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Jul 16th, 2019
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VHDL 3.54 KB | None | 0 0
  1. librarY ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. EntitY MealY_2 IS Port
  6. (
  7.   clk_input         : in  std_logic ;
  8.   rst_n                 : in  std_logic ;
  9.   pb_3              : in  std_logic;
  10.   extout                : in  std_logic ;
  11.   pb_2              : in std_logic;
  12.   XLT, XET, XGT, YLT, YET, YGT : in std_logic;
  13.   clk_en_X, clk_en_Y, U1_D0_X, U1_D0_Y, ext_en, error           : OUT std_logic
  14.   -- ,
  15.  
  16.  );
  17. END ENTITY;
  18.  
  19.  
  20.  Architecture SM of MealY_2 is
  21.  
  22.  
  23.  TYPE STATE_NAMES IS (IN_MOTION, ERROR_STATE);   -- list all the STATE_NAMES values but use more meaningful names
  24.  
  25.  
  26.  SIGNAL current_state, next_state   :  STATE_NAMES;         -- signals of tYpe STATE_NAMES
  27.  signal input_signals : std_logic_vector(4 downto 0);
  28.  
  29.  signal pb3         : std_logic;
  30.  
  31.  signal X_ET            : std_logic;
  32.  signal X_LT            : std_logic;
  33.  signal X_GT            : std_logic;
  34.  
  35.  signal pb2             : std_logic;
  36.  
  37.  signal Y_ET            : std_logic;
  38.  signal Y_LT            : std_logic;
  39.  signal Y_GT            : std_logic;
  40.  
  41.  signal ext_out     : std_logic;
  42.  
  43.  
  44.  BEGIN
  45.  
  46.   pb3 <= NOT pb_3;
  47.   X_LT <= XLT;
  48.   X_ET <= XET;
  49.   X_GT <= XGT;
  50.  
  51.   pb2 <= NOT pb_2;
  52.   Y_LT <= YLT;
  53.   Y_ET <= YET;
  54.   Y_GT <= YGT;
  55.  
  56.   ext_out <= extout;
  57.   ext_en   <= X_ET AND Y_ET;
  58.  
  59.  --------------------------------------------------------------------------------
  60.  --State Machine:
  61.  --------------------------------------------------------------------------------
  62.  
  63.  -- REGISTER_LOGIC PROCESS:
  64.  
  65. Register_Section: PROCESS (clk_input, rst_n)  -- this process sYnchronizes the activitY to a clock
  66. BEGIN
  67.     IF (rst_n = '0') THEN
  68.         current_state <= IN_MOTION;
  69.     ELSIF(rising_edge(clk_input)) THEN
  70.         current_state <= next_State;
  71.     END IF;
  72. END PROCESS;   
  73.  
  74.  
  75.  
  76. -- TRANSITION LOGIC PROCESS
  77.  
  78. Transition_Section: PROCESS (
  79.               pb3 ,
  80.               X_LT ,
  81.               X_ET ,
  82.               X_GT ,
  83.              
  84.               pb2 ,
  85.               Y_LT ,
  86.               Y_ET ,
  87.               Y_GT ,
  88.              
  89.               ext_out ,
  90.               current_state
  91.     )
  92.  
  93. BEGIN
  94.      CASE current_state IS
  95.           WHEN IN_MOTION =>     --this part can have 0 and 1??
  96.                 IF( ( ((pb3 = '1') AND (X_ET = '0')) OR ((pb2 = '1') AND (Y_ET = '0')) ) AND (ext_out = '1') ) THEN -- pb is pressed, X or Y not equal to target, extended
  97.                     next_state <= ERROR_STATE;
  98.                 ELSE
  99.                     next_state <= IN_MOTION;  -- staY in the same state otherwise
  100.                 END IF;    
  101.                
  102.              WHEN ERROR_STATE =>
  103.                 IF(
  104.                     ext_out = '0'
  105.                 ) THEN -- the onlY waY to eXit the error state is when You toggle the extender OFF
  106.                     next_state <= IN_MOTION;
  107.                 ELSE
  108.                     next_state <= ERROR_STATE; -- otherwise staY
  109.                 END IF;
  110.                
  111.                 WHEN OTHERS =>
  112.                next_state <= IN_MOTION;
  113.         END CASE;
  114.  
  115.  
  116.  END PROCESS;
  117.  
  118. -- DECODER SECTION PROCESS
  119.  
  120. Decoder_Section: PROCESS (   
  121.               pb3 ,
  122.               X_LT ,
  123.               X_ET ,
  124.               X_GT ,
  125.              
  126.               pb2 ,
  127.               Y_LT ,
  128.               Y_ET ,
  129.               Y_GT ,
  130.              
  131.               ext_out ,
  132.               current_state)
  133.  
  134. BEGIN
  135.      
  136.      
  137.      CASE current_state IS
  138.      
  139.          WHEN IN_MOTION =>      -- make sure You have code to actuallY staY in error state
  140.                     clk_en_X <= (NOT X_ET) AND pb3 AND NOT ext_out;
  141.                     clk_en_Y <= (NOT Y_ET) AND pb2 AND NOT ext_out;
  142.                     U1_D0_X  <=  X_LT; -- You don't care about these values unless the clock is enabled, which onlY happens when not equal
  143.                     U1_D0_Y  <=  Y_LT;
  144.                     --error    <=  (pb3 AND (X_LT OR X_GT)) OR (pb2 AND (Y_LT OR Y_GT ));
  145.                     error      <= '0';
  146.            
  147.             WHEN ERROR_STATE =>
  148.                     error      <= '1';
  149.                    
  150.             WHEN OTHERS =>
  151.                     clk_en_X <= '0';
  152.                     clk_en_Y <= '0';
  153.                     U1_D0_X  <= '0';
  154.                     U1_D0_Y  <= '0';
  155.                     error      <= '0';
  156.            
  157.       END CASE;
  158.      
  159.  END PROCESS;
  160.  
  161.  END ARCHITECTURE SM;
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