uart_byte_collector

LIBRARY ieee;
use ieee.numeric_std.all;
use IEEE.std_logic_1164.all;

ENTITY uart_byte_collector IS
    PORT(
            rst                     :   in  std_logic;
            clk                     :   in  std_logic;

            rx_dv                   :   in  std_logic;
            rx_byte                 :   in  std_logic_vector(7 downto 0);

            ready                   :   out std_logic;

            byte0                   :   out std_logic_vector(7 downto 0);
            byte1                   :   out std_logic_vector(7 downto 0);
            byte2                   :   out std_logic_vector(7 downto 0);
            byte3                   :   out std_logic_vector(7 downto 0);
            byte4                   :   out std_logic_vector(7 downto 0);
            byte5                   :   out std_logic_vector(7 downto 0)
        );
END ENTITY uart_byte_collector;

ARCHITECTURE behavioural OF uart_byte_collector IS

    signal byte_counter : integer range 0 to 6;
    type byte_array is array (0 to 5) of std_logic_vector(7 downto 0);
    signal serial_byte : byte_array;
    signal time_out_counter : integer range 0 to 66500000;
    signal time_out_counter_enable, time_out_flag : std_logic;

    signal data_ready   :   std_logic;
begin

    collect_bytes : process (rst, clk) is
    begin
        if rst = '1' then
            serial_byte <= (others => (others => '0'));
            byte_counter <= 0;
            time_out_counter_enable <= '0';
            data_ready <= '0';
        elsif rising_edge(clk) then
            if time_out_flag = '1' then
                serial_byte <= (others => (others => '0'));
                byte_counter <= 0;
                time_out_counter_enable <= '0';
                data_ready <= '0';
            elsif byte_counter < 6 then
                if rx_dv = '1' then
                    serial_byte(byte_counter) <= rx_byte;
                    byte_counter <= byte_counter + 1;
                    time_out_counter_enable <= '1';

                end if;
            else
                if data_ready = '0' then
                    data_ready <= '1';
                    time_out_counter_enable <= '0';
                else
                    serial_byte <= (others => (others => '0'));
                    byte_counter <= 0;
                    data_ready <= '0';
                end if;

            end if;

        end if;
    end process;



    timeout : process (rst, clk) is
    begin
        if rst = '1' then
            time_out_counter <= 0;
            time_out_flag <= '0';
        elsif rising_edge(clk) then
            if time_out_flag = '0' then
                if time_out_counter_enable = '1' then
                    time_out_counter <= time_out_counter + 1;
                    if time_out_counter = 66500000 then
                        time_out_flag <= '1';
                        time_out_counter <= 0;
                    end if;
                else
                    time_out_counter <= 0;
                    time_out_flag <= '0';
                end if;

            else
                time_out_counter <= 0;
                time_out_flag <= '0';

            end if;
        end if;
    end process;


    ready <= data_ready;

    byte0 <= serial_byte(0);
    byte1 <= serial_byte(1);
    byte2 <= serial_byte(2);
    byte3 <= serial_byte(3);
    byte4 <= serial_byte(4);
    byte5 <= serial_byte(5);

end architecture behavioural;