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Jun 28th, 2018
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VHDL 2.58 KB | None | 0 0
  1. entity Memoria is
  2. Port (                  
  3.     clk : in  STD_LOGIC;        
  4.     reset : in  STD_LOGIC;
  5.     writeENABLE: in STD_LOGIC;
  6.     cs: in STD_LOGIC;
  7.     endereco: in STD_LOGIC_VECTOR(4 downto 0);
  8.     dados_in : in STD_LOGIC_VECTOR(9 downto 0);
  9.     dados_out : out STD_LOGIC_VECTOR(9 downto 0);
  10.     dados_trinta : out STD_LOGIC_VECTOR(9 downto 0));
  11. end Memoria;
  12.  
  13. architecture Behavioral of Memoria is
  14.     type ram_mem is array (0 to 31) of std_logic_vector(9 downto 0);
  15.     --signal DATA : ram_mem := (others => (others => '0'));
  16.     signal DATA: ram_mem :=
  17.                 --registradores inicializam em 1
  18.         (      0 => "0000110001", --move from 17 to A
  19.                  1 => "0010000000", --move from A to B
  20.                  2 => "0000110010", --move from 18 to A
  21.                  3 => "0011100000", --and A e B
  22.                  4 => "0001011110", --copy from A to 30
  23.                  5 => "0010100000", --add A e B
  24.                  6 => "0011000000", --sub A e B
  25.                  7 => "0101000000", --not A
  26.                  8 => "0100000000", --or A e B
  27.                  9 => "0101000000", --not A
  28.                  10 => "0110011001", --jump Z to 25
  29.                  17 => "0000000010", --conteudo a ficar no B
  30.                  18 => "1111100010", --conteudo a ficar no A
  31.                  19 => "0000000100", --conteudo a ficar no A no fim
  32.                  25 => "0000110011", --move from 19 to A       
  33.                  26 => "0001011110", --copy from A to 30                 
  34.          others => "0000000000");
  35.     signal read_address : std_logic_vector(endereco'range);
  36. begin
  37.  
  38.     --Teste 1
  39. --  signal DATA: ram_mem :=
  40. --      (      0 => "0010100000", --add1
  41. --               1 => "0011000000", --sub1
  42. --               2 => "0001011110", --copy to 30
  43. --               3 => "0011000000", --sub1
  44. --               4 => "0011000000", --sub1
  45. --               5 => "0110101010", --jump n
  46. --               10 => "0000111110", --copy from 30
  47. --         others => "0000000000");
  48.  
  49.     --Teste 2
  50. --signal DATA: ram_mem :=
  51. --              --registradores inicializam em 1
  52. --      (      0 => "0010100000", --add1
  53. --               1 => "0011000000", --sub1
  54. --               2 => "0001011110", --copy to 30
  55. --               3 => "0011000000", --sub1
  56. --               4 => "0110001010", --jump z
  57. --               5 => "0110101010", --jump n (nao sera executado)
  58. --               10 => "0000110100", --copy from 20
  59. --               11 => "0001011110", --copy to 30
  60. --               20 => "0000000101", --data = 5
  61. --         others => "0000000000");
  62.  
  63.  
  64.  
  65. dados_out <= DATA(to_integer(unsigned(read_address)));
  66. dados_trinta <= DATA(30);
  67.  
  68. process(clk, reset)
  69. begin
  70.    
  71.    
  72.     if rising_edge(clk) then
  73.         if reset = '1' then
  74.             DATA <= (others => (others => '0'));
  75.         else
  76.             read_address <= endereco;
  77.             if cs = '1' then
  78.                 if (writeENABLE = '1') then
  79.                     DATA(to_integer(unsigned(endereco))) <= dados_in;
  80.                 end if;
  81.             end if;
  82.         end if;
  83.     end if;
  84. end process;
  85.  
  86. end Behavioral;
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