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- entity Memoria is
- Port (
- clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- writeENABLE: in STD_LOGIC;
- cs: in STD_LOGIC;
- endereco: in STD_LOGIC_VECTOR(4 downto 0);
- dados_in : in STD_LOGIC_VECTOR(9 downto 0);
- dados_out : out STD_LOGIC_VECTOR(9 downto 0);
- dados_trinta : out STD_LOGIC_VECTOR(9 downto 0));
- end Memoria;
- architecture Behavioral of Memoria is
- type ram_mem is array (0 to 31) of std_logic_vector(9 downto 0);
- --signal DATA : ram_mem := (others => (others => '0'));
- signal DATA: ram_mem :=
- --registradores inicializam em 1
- ( 0 => "0000110001", --move from 17 to A
- 1 => "0010000000", --move from A to B
- 2 => "0000110010", --move from 18 to A
- 3 => "0011100000", --and A e B
- 4 => "0001011110", --copy from A to 30
- 5 => "0010100000", --add A e B
- 6 => "0011000000", --sub A e B
- 7 => "0101000000", --not A
- 8 => "0100000000", --or A e B
- 9 => "0101000000", --not A
- 10 => "0110011001", --jump Z to 25
- 17 => "0000000010", --conteudo a ficar no B
- 18 => "1111100010", --conteudo a ficar no A
- 19 => "0000000100", --conteudo a ficar no A no fim
- 25 => "0000110011", --move from 19 to A
- 26 => "0001011110", --copy from A to 30
- others => "0000000000");
- signal read_address : std_logic_vector(endereco'range);
- begin
- --Teste 1
- -- signal DATA: ram_mem :=
- -- ( 0 => "0010100000", --add1
- -- 1 => "0011000000", --sub1
- -- 2 => "0001011110", --copy to 30
- -- 3 => "0011000000", --sub1
- -- 4 => "0011000000", --sub1
- -- 5 => "0110101010", --jump n
- -- 10 => "0000111110", --copy from 30
- -- others => "0000000000");
- --Teste 2
- --signal DATA: ram_mem :=
- -- --registradores inicializam em 1
- -- ( 0 => "0010100000", --add1
- -- 1 => "0011000000", --sub1
- -- 2 => "0001011110", --copy to 30
- -- 3 => "0011000000", --sub1
- -- 4 => "0110001010", --jump z
- -- 5 => "0110101010", --jump n (nao sera executado)
- -- 10 => "0000110100", --copy from 20
- -- 11 => "0001011110", --copy to 30
- -- 20 => "0000000101", --data = 5
- -- others => "0000000000");
- dados_out <= DATA(to_integer(unsigned(read_address)));
- dados_trinta <= DATA(30);
- process(clk, reset)
- begin
- if rising_edge(clk) then
- if reset = '1' then
- DATA <= (others => (others => '0'));
- else
- read_address <= endereco;
- if cs = '1' then
- if (writeENABLE = '1') then
- DATA(to_integer(unsigned(endereco))) <= dados_in;
- end if;
- end if;
- end if;
- end if;
- end process;
- end Behavioral;
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