(NEW)dvb_s2x_interleaver.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
--use ieee.std_logic_arith.all;

entity dvb_s2x_interleaver is
    Port(
        i_clk             :  in  std_logic;                              -- тактирование
        i_res             :  in  std_logic;                              -- сброс
        i_enb             :  in  std_logic;                              -- разрешение работы
        i_QAM_select      :  in  std_logic_vector (2 downto 0);          -- выбор модуляции
        i_frame_select    :  in  std_logic_vector (0 downto 0);          -- выбор фрейма
        i_data            :  in  std_logic_vector (0 downto 0);          -- входные данные
        o_data            :  out std_logic_vector (0 downto 0));         -- выходные данные
end entity;

architecture Behavioral of dvb_s2x_interleaver is

    type Memory     is array (0 to 64805)     of std_logic_vector (0 downto 0);   -- память

    type LUT_add    is array (0 to 1, 0 to 6) of std_logic_vector(15 downto 0);                         -- границы для генератора и счетчика
    type LUT_Modulo is array (0 to 1, 0 to 6) of std_logic_vector(15 downto 0);                         -- значение модулей для фреймов

    constant add_LUT    : LUT_add    := (0 => (0 => "0000000000000001", 1 => "0101010001100000", 2 => "0011111101001000",
                                               3 => "0011001010100000", 4 => "0010101000110000", 5 => "0010010000101010",
                                               6 => "0001111110100100"),
                                         1 => (0 => "0000000000000001", 1 => "0001010100011000", 2 => "0000111111010010",
                                               3 => "0000110010101000", 4 => (others => '0'), 5 => (others => '0'), 6 => (others => '0')));
    constant Modulo_LUT : LUT_Modulo := (0 => (0 => "1111110100011111", 1 => "1111110100011111", 2 => "1111110100011111",
                                               3 => "1111110100011111", 4 => "1111110100011111", 5 => "1111110100100101",
                                               6 => "1111110100011111"),
                                         1 => (0 => "0011111101000111",1 => "0011111101000111", 2 => "0011111101000111", 3 => "0011111101000111",
                                               4 => (others => '0'), 5 => (others => '0'),  6 => (others => '0')));

    signal interleaver_0       :  Memory;
    signal interleaver_1       :  Memory;
    signal address_0           :  std_logic_vector(15 downto 0);
    signal address_1           :  std_logic_vector(15 downto 0);
    signal WE_0                :  std_logic;
    signal WE_1                :  std_logic;
    signal modulo_0            :  std_logic_vector(15 downto 0);
    signal add_0               :  std_logic_vector(15 downto 0);
    signal sub_0               :  std_logic_vector(15 downto 0);
    signal compare_0           :  std_logic_vector(15 downto 0);
    signal modulo_1            :  std_logic_vector(15 downto 0);
    signal add_1               :  std_logic_vector(15 downto 0);
    signal sub_1               :  std_logic_vector(15 downto 0);
    signal compare_1           :  std_logic_vector(15 downto 0);
    signal frame_latch         :  std_logic_vector(0 downto 0);
    signal QAM                 :  std_logic_vector(2 downto 0);
    signal out_0               :  std_logic_vector(0 downto 0);
    signal out_1               :  std_logic_vector(0 downto 0);


    component dvb_s2x_RAM
        Port(
            clk       : in std_logic;
            res       : in std_logic;
            WE        : in std_logic;
            address   : in std_logic_vector(15 downto 0);
            in_data   : in std_logic_vector(0 downto 0);
            out_data  : out std_logic_vector(0 downto 0));
    end component;

begin

RAM_0: dvb_s2x_RAM
    -- for address_0
    port map(
        clk      =>  i_clk,
        res      =>  i_res,
        WE       =>  WE_0,
        address  =>  address_0,
        in_data  =>  i_data,
        out_data =>  out_0);
RAM_1: dvb_s2x_RAM
    -- for address_1
    port map(
        clk      =>  i_clk,
        res      =>  i_res,
        WE       =>  WE_1,
        address  =>  address_1,
        in_data  =>  i_data,
        out_data =>  out_1);


main:process(i_clk)

begin
if(rising_edge(i_clk)) then
    if(i_enb = '1') then
        if(WE_0 = '0') then
            o_data <= interleaver_0(to_integer(unsigned(address_0)));
            if(address_0 = modulo_0) then
                address_0 <= (others => '0');
                WE_0      <= '1';
            elsif(unsigned(address_0) = 0) then
                address_0 <= std_logic_vector(unsigned(address_0) + unsigned(add_0));
            elsif(unsigned(address_0) < unsigned(compare_0)) then
                address_0 <= std_logic_vector(unsigned(address_0) + unsigned(add_0));
            else
                address_0 <= std_logic_vector(unsigned(address_0) - unsigned(sub_0));
            end if;
        else
            QAM                      <= i_QAM_select;
            modulo_0                 <= Modulo_LUT(to_integer(unsigned(frame_latch)), to_integer(unsigned(QAM)));
            add_0                    <= add_LUT(to_integer(unsigned(frame_latch)), to_integer(unsigned(QAM)));
            sub_0                    <= std_logic_vector(unsigned(modulo_0) - unsigned(add_0));
            compare_0                <= std_logic_vector(unsigned(modulo_0) - unsigned(add_0) + 1);
            interleaver_0(to_integer(unsigned(address_0))) <= i_data;
            if(address_0 = modulo_0) then
                address_0 <= (others => '0');
                WE_0      <= '0';
                WE_1      <= '1';
            else
                address_0 <= std_logic_vector(unsigned(address_0) + 1);
            end if;
        end if;
                --
        if(WE_1 = '0') then
            o_data <= interleaver_1(to_integer(unsigned(address_1)));
            if(address_1 = modulo_1) then
                address_1 <= (others => '0');
                WE_1      <= '1';
            elsif(unsigned(address_1) = 0) then
                address_1 <= std_logic_vector(unsigned(address_1) + unsigned(add_1));
            elsif(unsigned(address_1) < unsigned(compare_1)) then
                address_1 <= std_logic_vector(unsigned(address_1) + unsigned(add_1));
            else
                address_1 <= std_logic_vector(unsigned(address_1) - unsigned(sub_1));
            end if;
        else
            QAM                      <= i_QAM_select;
            modulo_1                 <= Modulo_LUT(to_integer(unsigned(frame_latch)), to_integer(unsigned(QAM)));
            add_1                    <= add_LUT(to_integer(unsigned(frame_latch)), to_integer(unsigned(QAM)));
            sub_1                    <= std_logic_vector(unsigned(modulo_1) - unsigned(add_1));
            compare_1                <= std_logic_vector(unsigned(modulo_1) - unsigned(add_1) + 1);
            interleaver_1(to_integer(unsigned(address_1))) <= i_data;
            if(address_1 = modulo_1) then
                address_1 <= (others => '0');
                WE_1      <= '0';
                WE_0      <= '1';
            else
                address_1 <= std_logic_vector(unsigned(address_1) + 1);
            end if;
        end if;
    else
        if(i_res = '1') then
            QAM                <= i_QAM_select;
            frame_latch        <= i_frame_select;
            modulo_0           <= Modulo_LUT(to_integer(unsigned(frame_latch)), to_integer(unsigned(QAM)));
            modulo_1           <= Modulo_LUT(to_integer(unsigned(frame_latch)), to_integer(unsigned(QAM)));
            address_0          <= (others => '0');
            address_1          <= (others => '0');
            WE_0               <='1';
            WE_1               <='0';
            add_0              <= (others => '0');
            add_1              <= (others => '0');
            sub_0              <= std_logic_vector(unsigned(modulo_0) - unsigned(add_0));
            sub_1              <= std_logic_vector(unsigned(modulo_1) - unsigned(add_1));
            compare_0          <= std_logic_vector(unsigned(modulo_0) - unsigned(add_0) + 1);
            compare_1          <= std_logic_vector(unsigned(modulo_1) - unsigned(add_1) + 1);
        else end if;
    end if;
end if;
end process;
end architecture;