mux_decenas

library ieee;
use ieee.std_logic_1164.all;

entity mux_1 is
    port (
        bcd1 : in std_logic_vector(3 downto 0);
        SW9  : in std_logic_vector(1 downto 0);
        DC   : out std_logic_vector(3 downto 0)
    );
end mux_1;

architecture dataflow of mux_1 is

begin

    process (SW9, bcd1) is

    begin

        case SW9 is
            when "00" => DC <= "1001";
            when "01" => DC <= bcd1;
            when others => DC <= (others => '0');
        end case;

    end process;

end dataflow;