ALU

entity ALU is
    Port ( RdData1 : in  STD_LOGIC_VECTOR (15 downto 0);
           RdData2 : in  STD_LOGIC_VECTOR (15 downto 0);
              Clk : in STD_LOGIC;
           ALUOP : in  STD_LOGIC_VECTOR (2 downto 0);
           Y : out  STD_LOGIC_VECTOR (15 downto 0);
              C_En : in STD_LOGIC;
              Z_En : in STD_LOGIC;
              OV_En : in STD_LOGIC;
              N_En : in STD_LOGIC;
              C : out STD_LOGIC;
              Z : out STD_LOGIC;
              OV : out STD_LOGIC;
              N : out STD_LOGIC;
              CarryIN : in STD_LOGIC;
              SLlit : in STD_LOGIC_VECTOR (3 downto 0);
              BTST_bit4 : in STD_LOGIC_VECTOR (3 downto 0)
              );
end ALU;

architecture Behavioral of ALU is
    signal result   : std_logic_vector(16 downto 0);
    signal zero     : std_logic;
    signal overflow: std_logic;
    signal null_word:std_logic_vector(16 downto 0);

begin

    null_word <= x"0000"&b"0";

    with ALUOP select
        result <=   ((b"0"&RdData1) + (b"0"&RdData2)) when "000",
                        (("0"&RdData1) + ("0"&(not RdData2)) + 1) when "001",
                        ((b"0"&RdData1) and (b"0"&RdData2)) when "010",
                        ((b"0"&RdData1) or (b"0"&RdData2)) when "011",
                        (b"0"&RdData2(15 - conv_integer(SLlit) downto 0)&null_word(conv_integer(SLlit) - 1 downto 0)) when "100",
                        (b"0"&RdData2 + 1) when "101",
                        (b"0"&RdData2) + (b"0"&(not RdData1)) + 1 - (not CarryIN) when "110",
                        x"0000"&b"0" when others;

        Y <= result(15 downto 0);

        zero <= (not (RdData2(conv_integer(BTST_bit4)))) when ALUOP = "111" else
                    '1' when result(15 downto 0) = x"0000"
                    else '0';

        Z <= zero when rising_edge(Clk) and Z_En = '1';

        N <= result(15) when rising_edge(Clk) and N_En = '1';

        overflow <= '1' when    ((ALUOP = "000" and RdData1(15) = RdData2(15) and result(15) = (not RdData1(15))) or
                                         (ALUOP = "001" and RdData1(15) = (not RdData2(15)) and result(15) = RdData2(15)) or
                                         (ALUOP = "101" and RdData2 = (not result)) or
                                         (ALUOP = "110" and RdData1(15) = (not RdData2(15)) and result(15) = RdData1(15))) else
                        '0';

        OV <= overflow when rising_edge(Clk) and OV_En = '1';

        C <= result(16) when rising_edge(Clk) and C_En = '1';
end Behavioral;