library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity tp7 is
   port (
         clk, load: in std_logic;
         b: in std_logic_vector(7 downto 0);
         z, notz, dsel, dp: out std_logic);
end tp7;

architecture comp of tp7 is
type state is (par,impar);
signal st, nst: state;
signal w,p,clear,sel,d,dmux: std_logic;
signal c: std_logic_vector(2 downto 0);
signal aux: std_logic_vector (7 downto 0);
begin

    -- maquina de estado
    process (clk,load)
    begin
        if load = '1' then
            st<=par;
        elsif (clk'event and clk='1') then
            st<=nst;
        end if;
    end process;


    process (clk,w)
    begin
        case st is
            when par=>   if w='0' then
                            nst<=par;
                       else
                            nst<=impar;
                       end if;

            when impar=>   if w='0' then
                            nst<=impar;
                       else
                            nst<=par;
                       end if;
        end case;
    end process;

    process (st)
    begin
        if (st=par) then
            p<='0';
        else
            p<='1';
        end if;
    end process;


    --contador
    clear <= not load;
    process (clk,clear)
    begin
        if clear = '0' then
            c<=(others=>'0');
        elsif (clk'event and clk='1') then
            c<=c+1;
        end if;
    end process;

    --and
    process (c)
    begin
        sel <= c(0) and c(1) and c(2);
        dsel <= sel;
    end process;

    --mux
    process (p,w)
    begin
        if (sel='0') then
            dmux<=w;
        else
            dmux<=p;
        end if;
    end process;

    --ShiftRegister
    process (load, b, clk)
    begin
        if load = '1' then
            aux<=b;
        elsif (clk'event and clk='1') then
            aux(7) <= '0';
            for i in 6 downto 0 loop
                aux(i) <= aux(i+1);
            end loop;

        end if;w <= aux(0);
    end process;

    --FlipFlop
    process(clk, dmux)
    begin
      if (clk'event and clk='1') then
        z <= dmux;
        notz <= not dmux;
      end if;
    end process;


end comp;