7_segment

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity ledsa is
port (
clk_50MHz : in std_logic;
disp_7_num : out std_logic_vector (7 downto 0);
disp_7_bits : out std_logic_vector (7 downto 0);
);
end ledsa;

architecture key_led_arch of ledsa is
    signal Counter : std_logic_vector(23 downto 0);
    signal value_of_cell :std_logic_vector(3 downto 0);
    signal seven_segment_on :std_logic_vector(7 downto 0) := X"00";
    signal seven_segment_unit :std_logic_vector(2 downto 0) := "111";
    signal led_7_segment_number : std_logic_vector(31 downto 0) := X"00000000";

begin

    Prescaler : process(clk_50MHz)
    begin

    case value_of_cell is
    when X"0" =>   disp_7_num <= "00000011"; --0
    when X"1" =>   disp_7_num <= "10011111";
    when X"2" =>   disp_7_num <= "00100101"; --2
    when X"3" =>   disp_7_num <= "00001101";
    when X"4" =>   disp_7_num <= "10011001"; --4
    when X"5" =>   disp_7_num <= "01001001";
    when X"6" =>   disp_7_num <= "01000001"; --6
    when X"7" =>   disp_7_num <= "00011111";
    when X"8" =>   disp_7_num <= "00000001"; --8
    when X"9" =>   disp_7_num <= "00001001";
    when X"A" =>   disp_7_num <= "00010001"; --A
    when X"B" =>   disp_7_num <= "11000001";
    when X"C" =>   disp_7_num <= "01100011"; --C
    when X"D" =>   disp_7_num <= "10000101";
    when X"E" =>   disp_7_num <= "01100000"; --E
    when X"F" =>   disp_7_num <= "01110001";
    when others => disp_7_num <= "11111111";
    end case;

    case seven_segment_unit is
    when "000" =>
    disp_7_bits <= X"FE";
    value_of_cell <= led_7_segment_number(3 downto 0);
    when "001" =>
    disp_7_bits <= X"FD";
    value_of_cell <= led_7_segment_number(7 downto 4);
    when "010" =>
    disp_7_bits <= X"FB";
    value_of_cell <= led_7_segment_number(11 downto 8);
    when "011" =>
    disp_7_bits <= X"F7";
    value_of_cell <= led_7_segment_number(15 downto 12);
    when "100" =>
    disp_7_bits <= X"EF";
    value_of_cell <= led_7_segment_number(19 downto 16);
    when "101" =>
    disp_7_bits <= X"DF";
    value_of_cell <= led_7_segment_number(23 downto 20);
    when "110" =>
    disp_7_bits <= X"BF";
    value_of_cell <= led_7_segment_number(27 downto 24);
    when "111" =>
    disp_7_bits <= X"7F";
    value_of_cell <= led_7_segment_number(31 downto 28);
    end case;

    if rising_edge(clk_50MHz) then
            if Counter < 50000 then
                Counter <= Counter + 1;
            else
                Counter <= (others => '0');
                led_7_segment_number <= led_7_segment_number + 1;
                seven_segment_unit <= seven_segment_unit - 1;
                    if seven_segment_unit = "000" then
                        seven_segment_unit <= "111";
                    end if;
            end if;
        end if;

    end process Prescaler;

end architecture;