library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity memory is
Port ( DO: in STD_LOGIC_VECTOR(15 downto 0);
         A: in STD_LOGIC_VECTOR(31 downto 0);
         S_MAR: in STD_LOGIC;
         S_MBR: in STD_LOGIC;
         WR: in STD_LOGIC;
         RD: in STD_LOGIC;
         AD: out STD_LOGIC_VECTOR(31 downto 0);
         D: out STD_LOGIC_VECTOR(15 downto 0);
         DI: out STD_LOGIC_VECTOR(15 downto 0));

end memory;

architecture behaviour of memory is

signal MAR: STD_LOGIC_VECTOR(31 downto 0);
signal MBR: STD_LOGIC_VECTOR(15 downto 0);
signal bDI: STD_LOGIC_VECTOR(15 downto 0);

begin

process(DO, A, S_MAR, S_MBR, WR, RD) is



    begin

        if (S_MAR = '1') then MAR <= A; end if;--zapis adresu
        if (S_MBR = '1') then MBR <= DO; end if;    -- zapis danych
        if (RD = '1') then bDI <= MBR; end if; --odczyt z MBR do DI
        if (WR = '1') then MBR <= DO; --zapis z DO do MBR
        else MBR <= "ZZZZZZZZZZZZZZZZ";
        end if;


    end process;

DI <=bDI;
AD  <=MAR;
D  <=MBR;

end behaviour;