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- library ieee;
- use ieee.std_logic_1164.all;
- entity four_i_mux is
- port (
- in1 : in std_logic;
- in2 : in std_logic;
- in3 : in std_logic;
- in4 : in std_logic;
- sel1 : in std_logic;
- sel2 : in std_logic;
- result : out std_logic
- );
- end;
- architecture rt1 of four_i_mux is
- signal temp1, temp2, temp3, temp4 : std_logic;
- begin
- temp1 <= in1 and (not sel1 and not sel2);
- temp2 <= in2 and (sel1 and not sel2);
- temp3 <= in3 and (not sel1 and sel2);
- temp4 <= in4 and (sel1 and sel2);
- result <= (temp1 or temp2) or (temp3 or temp4);
- end;
- library ieee;
- use ieee.std_logic_1164.all;
- entity tb is end;
- architecture tb_arch of tb is
- component four_i_mux is
- port (
- in1 : in std_logic;
- in2 : in std_logic;
- in3 : in std_logic;
- in4 : in std_logic;
- sel1 : in std_logic;
- sel2 : in std_logic;
- result : out std_logic
- );
- end component;
- signal in1 : std_logic;
- signal in2 : std_logic;
- signal in3 : std_logic;
- signal in4 : std_logic;
- signal sel1 : std_logic;
- signal sel2 : std_logic;
- signal result : std_logic;
- begin
- entity_instance_1: four_i_mux
- port map(in1,in2,in3,in4,sel1,sel2,result);
- process is
- begin
- in1 <= '0';
- in2 <= '0';
- in3 <= '0';
- in4 <= '0';
- sel1 <= '0';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '1';
- in2 <= '0';
- in3 <= '0';
- in4 <= '0';
- sel1 <= '0';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '1';
- in3 <= '0';
- in4 <= '0';
- sel1 <= '0';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '0';
- in3 <= '1';
- in4 <= '0';
- sel1 <= '0';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '0';
- in3 <= '0';
- in4 <= '1';
- sel1 <= '0';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '0';
- in3 <= '0';
- in4 <= '0';
- sel1 <= '1';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '0';
- in3 <= '0';
- in4 <= '0';
- sel1 <= '0';
- sel2 <= '1';
- wait for 10 ps;
- in1 <= '1';
- in2 <= '1';
- in3 <= '0';
- in4 <= '0';
- sel1 <= '0';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '1';
- in3 <= '1';
- in4 <= '0';
- sel1 <= '0';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '0';
- in3 <= '1';
- in4 <= '1';
- sel1 <= '0';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '0';
- in3 <= '0';
- in4 <= '1';
- sel1 <= '1';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '0';
- in3 <= '0';
- in4 <= '0';
- sel1 <= '1';
- sel2 <= '1';
- wait for 10 ps;
- in1 <= '1';
- in2 <= '1';
- in3 <= '1';
- in4 <= '0';
- sel1 <= '0';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '1';
- in3 <= '1';
- in4 <= '1';
- sel1 <= '0';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '0';
- in3 <= '1';
- in4 <= '1';
- sel1 <= '1';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '0';
- in3 <= '0';
- in4 <= '1';
- sel1 <= '1';
- sel2 <= '1';
- wait for 10 ps;
- in1 <= '1';
- in2 <= '1';
- in3 <= '1';
- in4 <= '1';
- sel1 <= '0';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '1';
- in3 <= '1';
- in4 <= '1';
- sel1 <= '1';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '0';
- in3 <= '1';
- in4 <= '1';
- sel1 <= '1';
- sel2 <= '1';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '1';
- in3 <= '0';
- in4 <= '1';
- sel1 <= '0';
- sel2 <= '1';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '1';
- in3 <= '0';
- in4 <= '0';
- sel1 <= '1';
- sel2 <= '0';
- wait for 10 ps;
- in1 <= '0';
- in2 <= '0';
- in3 <= '1';
- in4 <= '0';
- sel1 <= '0';
- sel2 <= '1';
- wait for 10 ps;
- wait;
- end process;
- end;
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