Timer 2 channel 4 init

RCC->CFGR &= (RCC_CFGR_SW_1 | RCC_CFGR_SW_0); //Enable internal clock
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; //Enable tim3 clock
RCC->APB2ENR |= RCC_APB2ENR_IOPAEN;

GPIOA->CRL  |= GPIO_CRL_MODE3_1 | GPIO_CRL_MODE3_0; // 11: Output mode, max speed 50 MHz.
GPIOA->CRL  |= GPIO_CRL_CNF3_1 | GPIO_CRL_CNF3_0;  // 11: Alternate function output Open-drain

TIM2->CCMR2 |= (TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_0); // PWM mode 2 - In upcounting, channel 1 is inactive
TIM2->CCER  |= TIM_CCER_CC4E; // Capture/Compare 1 output to pin enable
TIM2->PSC    = 0xFFFF; // Prescaler value
TIM2->ARR    = 0x200; // ARR is the value to be loaded in the actual auto-reload register.
TIM2->CCR4   = 0x40; // Capture/Compare 1 value
TIM2->CR1   |= TIM_CR1_CEN; // Counter enable