SIGNAL start      : STD_LOGIC := '0';
begin

    process(clk) begin
        if rising_edge(clk) then
            if UART_Tx_start = '1' then
                start <= '1';
            elsif UART_clk_EN = '1' then
                pres_state       <= next_state;
                UART_Tx_data_out <= data_out;
                if (next_state = st_idle) then
                    UART_Tx_busy <= '0';
                else
                    UART_Tx_busy <= '1';
                end if;
                if start = '1' then
                    start <= '0';
                end if;
            end if;
        end if;
    end process;

    process (pres_state,start) begin
        case pres_state is
            when st_idle  =>
                if start = '1' then
                    next_state <= st_start;
                else
                    next_state <= st_idle;
                end if;
                data_out     <= '1';
            when st_start =>
                next_state <= st_b0;
                data_out   <= '0';
            when st_b0