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-- Company:
-- Engineer:
--
-- Create Date: 03/21/2018 12:27:21 PM
-- Design Name:
-- Module Name: sum_2biti - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
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-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sum_2biti is
    Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
           y : in STD_LOGIC_VECTOR (1 downto 0);
           S : out STD_LOGIC_VECTOR (1 downto 0);
           Tin : in STD_LOGIC;
           Pout : out STD_LOGIC;
           Gout : out STD_LOGIC);
end sum_2biti;

architecture Behavioral of sum_2biti is
signal g, p : STD_LOGIC_VECTOR(1 downto 0);
begin
    gp_process: process(x, y, Tin)
    begin
        for i in 1 downto 0 loop
           g(i) <= x(i) AND y(i);
           p(i) <= x(i) OR y(i);
        end loop;
    end gp_process;

    Gout <= g(1) OR p(1) AND g(0);
    Pout <= p(1) AND p(0);



end Behavioral;