VGA_Driver

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 -- Company:
 -- Engineer:
 --
 -- Create Date:    09:55:25 11/21/2014
 -- Design Name:
 -- Module Name:    Counter - Behavioral
 -- Project Name:
 -- Target Devices:
 -- Tool versions:
 -- Description:
 --
 -- Dependencies:
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 -- Revision:
 -- Revision 0.01 - File Created
 -- Additional Comments:
 --
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 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use ieee.std_logic_unsigned.all;

 -- Uncomment the following library declaration if using
 -- arithmetic functions with Signed or Unsigned values
 use IEEE.NUMERIC_STD.ALL;

 -- Uncomment the following library declaration if instantiating
 -- any Xilinx primitives in this code.
 --library UNISIM;
 --use UNISIM.VComponents.all;

 entity VGADriver is
      Port ( Reset : in  STD_LOGIC;
                CLK50 : in  STD_LOGIC;
                Up, Left, Down, Right : in STD_LOGIC;
                R, G, B, Hsync, Vsync : out STD_LOGIC);
 end VGADriver;

 architecture Behavioral of VGADriver is

 signal Add1, Add2 : STD_LOGIC_VECTOR(9 downto 0);
 signal Reg1, Reg2 : STD_LOGIC_VECTOR(9 downto 0);
 signal Mux1, Mux2 : STD_LOGIC_VECTOR(9 downto 0);
 signal Cmp1, Cmp2 : STD_LOGIC;

 signal Rows : STD_LOGIC_VECTOR(9 downto 0) := "1100100000";
 signal Columns : STD_LOGIC_VECTOR(9 downto 0) := "1000001001";

 signal CLK : STD_LOGIC;

 signal posX : STD_LOGIC_VECTOR(9 downto 0) := "0010010000";
 signal posY : STD_LOGIC_VECTOR(9 downto 0) := "0000011111";


 begin


--posX <= posX + 1 when Right = '1' else posX - 1 when Left = '1';
--posY <= posY + 1 when Down = '1'  else posY - 1 when Up = '1';

CLK <= not(CLK) when rising_edge(CLK50);

Hsync <= '0' when 0 <= Reg1 and Reg1 < 94 else '1';

Vsync <= '0' when 0 <= Reg2 and Reg2 < 2 else '1';

R <= '0' when (0 <= Reg1 and Reg1 < 144) OR (144+640 <= Reg1 and Reg1 < 144+640+16) OR (0 <= Reg2 and Reg2 < 31) OR (31+480 <= Reg2 and Reg2 < 31+480+10);
B <= '0' when (0 <= Reg1 and Reg1 < 144) OR (144+640 <= Reg1 and Reg1 < 144+640+16) OR (0 <= Reg2 and Reg2 < 31) OR (31+480 <= Reg2 and Reg2 < 31+480+10);
G <= '0' when (0 <= Reg1 and Reg1 < 144) OR (144+640 <= Reg1 and Reg1 < 144+640+16) OR (0 <= Reg2 and Reg2 < 31) OR (31+480 <= Reg2 and Reg2 < 31+480+10) else
        '1' when (posX <= Reg1 and Reg1 < posX+16) and (posY <= Reg2 and Reg2 < posY+16) else
        '0';


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 Add1 <= Reg1 + "0000000001";

 Mux1 <= Add1 when Cmp1 = '0' else "0000000000" when Cmp1 = '1';

 Cmp1 <= '1' when Add1 > Rows else '0';

 Reg1 <= "0000000000" when Reset = '0' else Mux1 when rising_edge(CLK);

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 Add2 <= Reg2 + "0000000001";

 Mux2 <= "0000000000" when Cmp2 = '1' and Cmp1='1' else
         Add2 when Cmp2 = '0' and Cmp1 = '1' else
            Reg2;

 Cmp2 <= '1' when Add2 > Columns else '0';

 Reg2 <= "0000000000" when Reset = '0' else Mux2 when rising_edge(CLK);

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 end Behavioral;