library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- CPOL0 (Idle CLK = 0)
-- CPHA1 (Change on rising edge, sampling on falling)

entity spimaster is
  port (
    CLK_IN           : in  std_logic;
    DATA_IN_H        : in  std_logic_vector(7 downto 0);
    DATA_IN_L        : in  std_logic_vector(7 downto 0);
    CS_OUT           : out std_logic;
    BUSY_FLAG        : out std_logic;
    MOSI             : out std_logic;
    ENABLE           : in  std_logic;
    SEND_CONFIG      : in  std_logic;
    CONFIG_BIT_STATE : in  std_logic;
    SPI_CLK          : out std_logic
    );
end entity;

architecture arch of spimaster is
begin

  process(CLK_IN)
  begin
    if(rising_edge(CLK_IN)) then

    end if;
  end process;



end architecture;