uas_arduino

Sigma Delta Test

May 11th, 2014
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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use ieee.numeric_std.all;
  4.  
  5. library unisim;
  6. use unisim.vcomponents.all;
  7.  
  8. entity SigmaDelta is
  9.     Port ( clk : in  STD_LOGIC;
  10.            rst : in  STD_LOGIC;
  11.            diff_n : in  STD_LOGIC;
  12.            diff_p : in  STD_LOGIC;
  13.            o : out  STD_LOGIC;
  14.               leds : out std_logic_vector(7 downto 0);
  15.               dac : out std_logic_vector(7 downto 0));
  16. end SigmaDelta;
  17.  
  18. architecture Behavioral of SigmaDelta is
  19.  
  20.     signal o_buf : std_logic;
  21.     signal total : unsigned(10 downto 0) := (others => '0');
  22.     signal count : unsigned(31 downto 0) := (others => '0');
  23.     signal fast_clk : std_logic := '0';
  24.     component mult
  25. port
  26.  (-- Clock in ports
  27.   CLK_IN1           : in     std_logic;
  28.   -- Clock out ports
  29.   CLK_OUT1          : out    std_logic
  30.  );
  31. end component;
  32. begin
  33.  
  34.     ibufds_inst : IBUFDS
  35.     generic map (
  36.         IOSTANDARD => "LVDS_25"
  37.     )
  38.     port map (
  39.         O => o_buf,
  40.         I => diff_p,
  41.         IB => diff_n
  42.     );
  43.    
  44.     your_instance_name : mult
  45.   port map
  46.    (-- Clock in ports
  47.     CLK_IN1 => clk,
  48.     -- Clock out ports
  49.     CLK_OUT1 => fast_clk);
  50.    
  51. --  process(clk, rst)
  52. --      variable counter : unsigned(31 downto 0) := (others => '0');
  53. --      type lut_type is array (0 to 255) of integer range 0 to 255;
  54. --      variable lut : lut_type := (127,130,133,136,139,142,145,148,151,154,157,160,163,166,169,172,175,178,181,184,186,189,192,194,197,200,202,205,207,209,212,214,216,218,221,223,225,227,229,230,232,234,235,237,239,240,241,243,244,245,246,247,248,249,250,250,251,252,252,253,253,253,253,253,254,253,253,253,253,253,252,252,251,250,250,249,248,247,246,245,244,243,241,240,239,237,235,234,232,230,229,227,225,223,221,218,216,214,212,209,207,205,202,200,197,194,192,189,186,184,181,178,175,172,169,166,163,160,157,154,151,148,145,142,139,136,133,130,127,123,120,117,114,111,108,105,102,99,96,93,90,87,84,81,78,75,72,69,67,64,61,59,56,53,51,48,46,44,41,39,37,35,32,30,28,26,24,23,21,19,18,16,14,13,12,10,9,8,7,6,5,4,3,3,2,1,1,0,0,0,0,0,0,0,0,0,0,0,1,1,2,3,3,4,5,6,7,8,9,10,12,13,14,16,18,19,21,23,24,26,28,30,32,35,37,39,41,44,46,48,51,53,56,59,61,64,67,69,72,75,78,81,84,87,90,93,96,99,102,105,108,111,114,117,120,123);
  55. --      variable lut_pos : unsigned(7 downto 0) := (others => '0');
  56. --  begin
  57. --      if(rst = '0') then
  58. --          counter := (others => '0');
  59. --          lut_pos := (others => '0');
  60. --      elsif(rising_edge(clk)) then
  61. --          if(counter = 50000000/6400) then
  62. --              dac <= std_logic_vector(to_unsigned(lut(to_integer(lut_pos)), 8));
  63. --              lut_pos := lut_pos + 1;
  64. --              counter := (others => '0');
  65. --          else
  66. --              counter := counter + 1;
  67. --          end if;
  68. --      end if;
  69. --  end process;
  70.    
  71.    
  72.     process(fast_clk, rst)
  73.         variable counter : unsigned(31 downto 0) := (others => '0');
  74.     begin
  75.         if(rst = '0') then
  76.             counter := (others => '0');
  77.             count <= (others => '0');
  78.             total <= (others => '0');
  79.             leds <= (others => '0');
  80.         elsif(rising_edge(fast_clk)) then
  81.             if(counter = (250000000/22000)/256) then
  82.                 counter := (others => '0');
  83.                 o <= o_buf;
  84.                 if(o_buf = '1') then
  85.                     total <= total + 1;
  86.                 end if;
  87.                 if(count = 2048) then
  88.                     leds <= std_logic_vector(total(10 downto 3));
  89.                     total <= (others => '0');
  90.                     count <= (others => '0');
  91.                     dac <= std_logic_vector(total(10 downto 3));
  92.                 else
  93.                     count <= count + 1;
  94.                 end if;
  95.             else
  96.                 counter := counter + 1;
  97.             end if;
  98.         end if;
  99.     end process;
  100.  
  101. end Behavioral;
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