--Exercise 6 tester--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;

entity Exercise6_tester is
port(
    SW : in std_logic_vector(17 downto 0);
    KEY: in std_logic_vector(3 downto 0);
    CLOCK_50: in std_logic;
    HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,LEDR : out std_logic_vector(6 downto 0)
);
end;

architecture test_1 of Exercise6_tester is
signal s1: std_logic_vector(3 downto 0);
begin
--UUT binary to seven seg display
UUT1: entity multi_counter port map
(mode => SW(17 downto 16), clk=>KEY(0),reset=>KEY(3),count=>s1, cout=>LEDR(0) );
UUT2: entity CaseBin2Sevenseg port map
(bin=>s1, sseg=>HEX0);
end;

architecture test_2 of Exercise6_tester is
signal clk_signal: std_logic;
signal s1: std_logic_vector(3 downto 0);
begin
--UUT clock_gen
UUT1: entity clock_gen port map
(speed=>KEY(0), clk=>CLOCK_50, reset=>KEY(3), clk_out=>clk_signal);
--UUT Multi_counter
UUT2: entity multi_counter port map
(mode => SW(17 downto 16), clk=>clk_signal,reset=>KEY(3),count=>s1, cout=>LEDR(0) );
--UUT bin to sevenseg display
UUT3: entity CaseBin2Sevenseg port map
(bin=>s1, sseg=>HEX0);
end;

architecture test_3 of Exercise6_tester is
begin
--UUT watch
UUT1: entity watch port map
(speed=>KEY(0), clk=>CLOCK_50,reset=>KEY(3),sec_1=>HEX0,sec_10=>HEX1,min_1=>HEX2,min_10=>HEX3,hrs_1=>HEX4,hrs_10=>HEX5, tm=>open);
end;