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baldengineer

ADC stuff

Dec 4th, 2011
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  1. /*
  2.  * ATmega32L_ADC_test.c
  3.  *
  4.  * Created: 03.12.2011 18:53:45
  5.  *  Author: Sabesto
  6.  */
  7.  
  8. #define F_CPU 8000000UL
  9. #define USART_BAUDRATE 9600
  10. #define BAUD_PRESCALE (((F_CPU / (USART_BAUDRATE * 16UL))) - 1)
  11.  
  12. #include <avr/io.h>
  13. #include <util/delay.h>
  14. #include <avr/interrupt.h>
  15.  
  16. volatile uint8_t newSampleReady = 0;
  17. volatile uint8_t channel = 0;
  18. volatile uint8_t ad[7];
  19.  
  20.  
  21. void uartinit (void)
  22. {
  23.     UCSRB |= (1 << RXEN) | (1 << TXEN);  
  24.     UCSRC |= (1 << UCSZ0) | (1 << UCSZ1);
  25.     UBRRH = (BAUD_PRESCALE >> 8);
  26.     UBRRL = BAUD_PRESCALE;
  27. }
  28. void USART1_Transmit(unsigned char data)
  29. {
  30.    while (!(UCSRA & (1<<UDRE)));                        
  31.    UDR = data;                
  32. }
  33. void USART1_TransmitString (const char *str) {
  34.  
  35.     while (*str)
  36.     {
  37.         USART1_Transmit(*str);
  38.         str++;
  39.     }    
  40. }
  41.  
  42. void adcinit (void){
  43.     ADCSRA |= (1 << ADPS2) | (1 << ADPS1); // | (1 << ADPS0); // Set ADC prescalar to 64(128) - 125KHz sample rate @ 16MHz
  44.     ADMUX = 0b01100000;
  45.     //ADMUX |= (1 << REFS0); // Set ADC reference to AVCC
  46.     //ADMUX |= (1 << ADLAR); // Left adjust ADC result to allow easy 8 bit reading
  47.     ADCSRA |= (1 << ADATE);  // Set ADC to Free-Running Mode
  48.     ADCSRA |= (1 << ADEN);  // Enable ADC
  49.     ADCSRA |= (1 << ADIE);  // enable adc interrupt
  50.     ADCSRA |= (1 << ADSC);  // Start A2D Conversions
  51.    
  52. }
  53. int main (void)
  54. {
  55.     uartinit();
  56.     adcinit();
  57.     sei();
  58.     while(1)
  59.     {
  60.         if (newSampleReady == 1)
  61.         {
  62.             for (uint8_t x = 0;x<7;x++)
  63.             {
  64.                 USART1_Transmit(ad[x]);
  65.                 _delay_ms(100);
  66.             }
  67.         _delay_ms(4000);
  68.         newSampleReady = 0;
  69.         ADCSRA |= (1<<ADIE);
  70.         }
  71.        
  72.     }
  73. }
  74.  
  75. ISR(ADC_vect)
  76. {
  77.     ad[channel] = ADCH; // Store the result (8-bits, discard the 3 LSB)
  78.     // ADCSRA &= ~(1 << ADEN); // Disable the ADC
  79.     channel ++;
  80.    
  81.        
  82.     if (channel == 7)
  83.     {
  84.         ADCSRA &= ~(1<<ADIE);
  85.         // disable interrupts for now
  86.         newSampleReady = 1; // 7 channels sampled
  87.         channel = 0; // Reset to channel 0
  88.     }  
  89.     ADMUX &= 0xE0;//Update the ADMUX register
  90.     ADMUX |= channel;
  91. }
  92.  
  93.  
  94.  
  95.    
  96.  
  97.  
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