count

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counters is
    port (clk, rst, enWr_A, enRd_A_1, enRd_A_3, enRd_A : in std_logic;
            mux_cnt : in std_logic_vector (1 downto 0);
            iseven_l, cnta_is1023_h, cntn_is0_h, cnt_Nis2, cnt_Nis1 : out std_logic;
            Address : out std_logic_vector (9 downto 0));
end counters;

architecture behavior of counters is

component CounterN is
    generic (N : integer := 10);
    port (Enable, Clk, Clear, up : in std_logic;
            Start : in unsigned (N-1 downto 0);
            Num                  : out std_logic_vector (N-1 downto 0));
end component;

component mux4to1 IS
    GENERIC ( N : POSITIVE := 10) ;
    PORT ( w0, w1, w2, w3  :      IN STD_LOGIC_VECTOR( ( N - 1 ) DOWNTO 0 ) ;
                  s           :       IN STD_LOGIC_VECTOR (1  DOWNTO 0) ;
                  f           :     OUT STD_LOGIC_VECTOR( ( N - 1 ) DOWNTO 0 ) ) ;
END component;

signal w0, w1, w2, w3, addr : std_logic_vector (9 downto 0);

begin
    cntW_A  : CounterN port map (Clk => clk, Enable => enWr_A,   Clear => rst, up => '1', Start => (others => '0'), Num => w0);
    cntRd_A_1: CounterN port map (Clk => clk, Enable => enRd_A_1, Clear => rst, up => '0', Start => "1111111110"   , Num => w1);
    cntRd_A : CounterN port map (Clk => clk, Enable => enRd_A,   Clear => rst, up => '0', Start => "1111111111" , Num => w2);
    cntRd_A_3: CounterN port map (Clk => clk, Enable => enRd_A_1, Clear => rst, up => '0', Start => "1111111100"    , Num => w3);

    mux_count   : mux4to1  port map (w0 => w0, w1 => w1, w2 => w2, w3 => w3, s => mux_cnt, f => Address);
    --Address <= unsigned(addr);

    iseven_l      <= w2(0);
    cnta_is1023_h <= (w0(9) and w0(8) and w0(7) and w0(6) and w0(5) and w0(4) and w0(3) and w0(2) and w0(1) and w0(0)); --'1' if first counter has finished
    cntn_is0_h <= (not w2(9) and not w2(8) and not w2(7) and not w2(6) and not w2(5) and not w2(4) and not w2(3) and not w2(2) and not w2(1) and not w2(0));    --'1' if counter (N count) has finished
    cnt_Nis2 <= (not w2(9) and not w2(8) and not w2(7) and not w2(6) and not w2(5) and not w2(4) and not w2(3) and not w2(2) and w2(1) and not w2(0));
    cnt_Nis1 <= (not w1(9) and not w1(8) and not w1(7) and not w1(6) and not w1(5) and not w1(4) and not w1(3) and not w1(2) and not w1(1) and not w1(0));
end behavior;