[VHDL] REGISTER 4-bit SIPO / TESTBENCH

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-- Company:
-- Engineer:
--
-- Create Date:   17:52:57 04/28/2017
-- Design Name:
-- Module Name:   C:/VHDL/_VEZBE_5/REGISTER_4BIT_SIPO/REGISTER_4BIT_PIPO_tb.vhd
-- Project Name:  REGISTER_4BIT_SIPO
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: REGISTER_4BIT_SIPO
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY REGISTER_4BIT_PIPO_tb IS
END REGISTER_4BIT_PIPO_tb;

ARCHITECTURE behavior OF REGISTER_4BIT_PIPO_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT REGISTER_4BIT_SIPO
    PORT(
         CLK : IN  std_logic;
         D : IN  std_logic;
         CE : IN  std_logic;
         WE : IN  std_logic;
         RE : IN  std_logic;
         CLEAR : IN  std_logic;
         PRESET : IN  std_logic;
         Q : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal CLK : std_logic := '0';
   signal D : std_logic := '0';
   signal CE : std_logic := '0';
   signal WE : std_logic := '0';
   signal RE : std_logic := '0';
   signal CLEAR : std_logic := '0';
   signal PRESET : std_logic := '0';

    --Outputs
   signal Q : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant CLK_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: REGISTER_4BIT_SIPO PORT MAP (
          CLK => CLK,
          D => D,
          CE => CE,
          WE => WE,
          RE => RE,
          CLEAR => CLEAR,
          PRESET => PRESET,
          Q => Q
        );

   -- Clock process definitions
   CLK_process :process
   begin
        CLK <= '0';
        wait for CLK_period/2;
        CLK <= '1';
        wait for CLK_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin

        CE <= '1', '0' after 500 ns;

        WE <= '0', '1' after 100ns;
        D <= '1', '0' after 110ns, '1' after 150ns, '0' after 200ns, '1' after 220ns, '0' after 250ns;
        RE <= '0', '1' after 190ns;

        PRESET <= '0', '1' after 300ns, '0' after 420ns;
        CLEAR <= '0', '1' after 400ns;

      wait;
   end process;

END;