VHDL LAB 5 CW6 RAM

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity RAM is
    port(
        key : IN STD_LOGIC;
        clk : IN STD_LOGIC :='1';
        sw  : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        wr  : IN STD_LOGIC;
        HEX0    : OUT STD_LOGIC_VECTOR (0 TO 6);
        HEX1    : OUT STD_LOGIC_VECTOR (0 TO 6)
    );
end RAM;

architecture rtl of RAM is
component RAM1PORT
    PORT
    (
        adres   : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
        clock   : IN STD_LOGIC :='1';
        data    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        wren    : IN STD_LOGIC;
        q   : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
    );
end component;

component hex7seg
    PORT (  hex : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        display : OUT STD_LOGIC_VECTOR (0 to 6)
    );
end component;

signal currentCount : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal output       : STD_LOGIC_VECTOR (7 DOWNTO 0);
alias bit3_0        : STD_LOGIC_VECTOR (3 DOWNTO 0) is output (3 downto 0);
alias bit7_4        : STD_LOGIC_VECTOR (3 DOWNTO 0) is output (7 downto 4);

signal HEXTMP0  :  STD_LOGIC_VECTOR (0 TO 6);
signal HEXTMP1  :  STD_LOGIC_VECTOR (0 TO 6);

begin

    MEM : RAM1PORT port map (adress=>currentCount, clock=>clk, data=>sw, wren=>wr,
        q=>output);
    SEG0: hex7seg port map (hex=>bit3_0, display=>HEXTMP0);
    SEG1: hex7seg port map (hex=>bit7_4, display=>HEXTMP1);

    process(key)
    begin
        if(key='0' and key'event) then
            if(currentCount="11111") then
                currentCount <= "00000";
            else
                currentCount <= currentCount + '1';
            end if;
        end if;
    end process;

    process(output)
    begin
        HEX0 <= HEXTMP0;
        HEX1 <= HEXTMP1;
    end process;

    process(output)
    begin
        HEX0 <= HEXTMP0;
        HEX1 <= HEXTMP1;
    end process;
end rtl;

-- EXTRAAAA DRUGI PLIK HEJKA

Library IEEE;
use ieee.std_logic_1164.all;

ENTITY hex7seg IS
    PORT (  hex : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        display : OUT STD_LOGIC_VECTOR (0 TO 6)
    );
end hex7seg;

ARCHITECTURE Behavior OF hex7seg IS
BEGIN
    PROCESS (hex)
    BEGIN
        CASE (hex) IS
            WHEN "0000" => display <= "0000001";
            WHEN "0001" => display <= "1001111";
            WHEN "0010" => display <= "0010010";
            WHEN "0011" => display <= "0000110";
            WHEN "0100" => display <= "1001100";
            WHEN "0101" => display <= "0100100";
            WHEN "0110" => display <= "1100000";
            WHEN "0111" => display <= "0001111";
            WHEN "1000" => display <= "0000000";
            WHEN "1001" => display <= "0001100";
            WHEN "0010" => display <= "0001000";
            WHEN "1011" => display <= "1100000";
            WHEN "1100" => display <= "0110001";
            WHEN "1101" => display <= "1000010";
            WHEN "1110" => display <= "0110000";
            WHEN OTHERS => display <= "0111000";
        END CASE;
    END PROCESS;
END Behavior;