icatalin

CN colocviu grup

May 23rd, 2019
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  1. module AND( in1, in2, out);
  2.  
  3. input in1, in2;
  4. output out;
  5.  
  6. assign out = (in1 & in2);
  7.  
  8. endmodule
  9.  
  10. //------------------------------------------------------------------------------
  11. module OR(in1,in2,out);
  12.  
  13. input in1,in2;
  14. output out;
  15.  
  16. assign out=(in1 | in2);
  17.  
  18. endmodule
  19. //------------------------------------------------------------------------------
  20. module NOT(in,out);
  21.  
  22. input in;
  23. output out;
  24.  
  25. assign out = ~(in);
  26.  
  27. endmodule
  28. //------------------------------------------------------------------------------
  29. module Testbench;
  30.  
  31. reg a,b,c;
  32. wire w1,w2,w3,w4,w5,out;
  33.  
  34.  
  35. initial begin
  36.  
  37. a = 0; b = 0; c=0;
  38. #1 c=1;
  39. #1 b=1;
  40. #1 c=0;
  41. #1 a=1;
  42. #1 b=0;
  43. #1 c=1;
  44. #1 b=1;
  45.  
  46. end
  47.  
  48. initial begin
  49. $monitor( "Time=%0d a=%b b=%b c=%b out=%b", $time, a, b, c, out);
  50. end
  51.  
  52.  
  53. NOT not_gate1(a,w1);
  54. OR or_gate1(b,c,w2);
  55. OR or_gate2(a,b,w3);
  56. NOT not_gate2(w3,w4);
  57. AND and_gate1(w1,w2,w5);
  58. OR or_gate3(w5,w4,out);
  59.  
  60. endmodule verilog
  61.  
  62.  
  63.  
  64.  
  65.  
  66.  
  67.  
  68. module XOR(A,B,S);
  69. input A, B;
  70. output reg S;
  71. always @ (A or B)
  72. begin
  73. S = A^B;
  74. end
  75. endmodule
  76.  
  77. module AND(A,B,S);
  78.  
  79. input A, B;
  80. output reg S;
  81. always @ (A or B)
  82. begin
  83. S = A & B;
  84. end
  85. endmodule
  86.  
  87. module halfadder;
  88.  
  89. reg A, B;
  90. output S, C;
  91. XOR myXOR(A,B,S);
  92. AND myAND(A,B,C);
  93. initial
  94. begin
  95. A = 0;
  96. B = 0;
  97. #1 $display("S=%b, C=%b\n",S,C);
  98. A = 0;
  99. B = 1;
  100. #1 $display("S=%b, C=%b\n",S,C);
  101. A = 1;
  102. B = 0;
  103. #1 $display("S=%b, C=%b\n",S,C);
  104. A = 1;
  105. B = 1;
  106. #1 $display("S=%b, C=%b\n",S,C);
  107. end
  108. endmodule
  109.  
  110.  
  111.  
  112.  
  113.  
  114.  
  115.  
  116.  
  117. .data
  118. matrice: .word 2, 5, 9, 10
  119. .word 1, 7, 4, 13
  120. .word 4, 6, 3, 9
  121. .word 12, 10, 9, 7
  122.  
  123.  
  124. .text
  125. .globl main
  126. main:
  127. la $a0, matrice
  128.  
  129. jal suma_matrice
  130.  
  131. li $v0, 1
  132. move $a0, $t0
  133. syscall
  134.  
  135. li $v0, 10
  136. syscall
  137. .end main
  138.  
  139.  
  140. suma_matrice:
  141. li $t0, 0
  142. li $t1, 4
  143. li $t2, 8
  144.  
  145. bucla:
  146. mul $t3, $t1, 4
  147. add $t3, $t3, $a0
  148. lw $t4, ($t3)
  149. add $t0, $t0, $t4
  150. addi $t1, $t1, 1
  151. blt $t1, $t2, bucla
  152. jr $ra
  153.  
  154. .end suma_matrice
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