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- module AND( in1, in2, out);
- input in1, in2;
- output out;
- assign out = (in1 & in2);
- endmodule
- //------------------------------------------------------------------------------
- module OR(in1,in2,out);
- input in1,in2;
- output out;
- assign out=(in1 | in2);
- endmodule
- //------------------------------------------------------------------------------
- module NOT(in,out);
- input in;
- output out;
- assign out = ~(in);
- endmodule
- //------------------------------------------------------------------------------
- module Testbench;
- reg a,b,c;
- wire w1,w2,w3,w4,w5,out;
- initial begin
- a = 0; b = 0; c=0;
- #1 c=1;
- #1 b=1;
- #1 c=0;
- #1 a=1;
- #1 b=0;
- #1 c=1;
- #1 b=1;
- end
- initial begin
- $monitor( "Time=%0d a=%b b=%b c=%b out=%b", $time, a, b, c, out);
- end
- NOT not_gate1(a,w1);
- OR or_gate1(b,c,w2);
- OR or_gate2(a,b,w3);
- NOT not_gate2(w3,w4);
- AND and_gate1(w1,w2,w5);
- OR or_gate3(w5,w4,out);
- endmodule verilog
- module XOR(A,B,S);
- input A, B;
- output reg S;
- always @ (A or B)
- begin
- S = A^B;
- end
- endmodule
- module AND(A,B,S);
- input A, B;
- output reg S;
- always @ (A or B)
- begin
- S = A & B;
- end
- endmodule
- module halfadder;
- reg A, B;
- output S, C;
- XOR myXOR(A,B,S);
- AND myAND(A,B,C);
- initial
- begin
- A = 0;
- B = 0;
- #1 $display("S=%b, C=%b\n",S,C);
- A = 0;
- B = 1;
- #1 $display("S=%b, C=%b\n",S,C);
- A = 1;
- B = 0;
- #1 $display("S=%b, C=%b\n",S,C);
- A = 1;
- B = 1;
- #1 $display("S=%b, C=%b\n",S,C);
- end
- endmodule
- .data
- matrice: .word 2, 5, 9, 10
- .word 1, 7, 4, 13
- .word 4, 6, 3, 9
- .word 12, 10, 9, 7
- .text
- .globl main
- main:
- la $a0, matrice
- jal suma_matrice
- li $v0, 1
- move $a0, $t0
- syscall
- li $v0, 10
- syscall
- .end main
- suma_matrice:
- li $t0, 0
- li $t1, 4
- li $t2, 8
- bucla:
- mul $t3, $t1, 4
- add $t3, $t3, $a0
- lw $t4, ($t3)
- add $t0, $t0, $t4
- addi $t1, $t1, 1
- blt $t1, $t2, bucla
- jr $ra
- .end suma_matrice
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