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kappabox 2020-24-06

crabb Jun 24th, 2020 (edited) 1,755 Never
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  1. /********************************************************************
  2.  *                   KAPPA BOX for SEGA SATURN
  3.  *           a header useful for sega saturn developers
  4.  *                    BY suwacrab 2020-21-06
  5.  *                   REVISION DATE 2020-23-06
  6.  ********************************************************************/
  7. /*                             TODO
  8.  * >           make function to load data from the CD
  9.  * >           remove SGL dependencies
  10. *********************************************************************/
  11. /*                             LOG
  12.  * >           2020-21-06: development begin: DMA
  13.  *             and type definitions!
  14.  * >           2020-24-06: CD Block start...
  15. *********************************************************************/
  16. #ifndef KBOX_H
  17. #define KBOX_H
  18.  
  19. #include "sgl_cd.h"
  20.  
  21. /*----- type defines ------------------------------------------------*/
  22. typedef unsigned char u8;
  23. typedef unsigned short u16;
  24. typedef unsigned int u32;
  25.  
  26. typedef signed char s8;
  27. typedef signed short s16;
  28. typedef signed int s32;
  29.  
  30. #define INLINE static inline
  31. #define PACKED   __attribute__((packed))
  32. #define ALIGN(n) __attribute__((aligned(n)))
  33.  
  34. /*---- color defines ------------------------------------------------*/
  35. typedef u16 CLR16; // 16-bit color in format 1BBBBBGGGGGRRRRR
  36. typedef struct CLR24 { u8 r,g,b; } PACKED CLR24; // 24-bit color
  37. INLINE CLR16 RGB16(u32 r,u32 g,u32 b)
  38. { return r | (g<<5) | (b<<10) | 0x8000; }
  39.  
  40. /*----- RAM defines -------------------------------------------------*/
  41. #define WRAM_LO  ((volatile u8*)(0x20200000))
  42. #define VDP1_MEM ((volatile u16*)(0x25C00000))
  43. #define SCU_MEM  ((volatile u8*)(0x25FE0000))
  44. #define WRAM_HI  ((volatile u8*)(0x26000000))
  45. #define DMA_MEM  ((volatile u8*)(0xFFFFFF80))
  46.  
  47. /*----- SH2 DMA defines ---------------------------------------------*/
  48. // > used for quickly copying data from one place to another, with
  49. // > the power of Hardware:tm:
  50.  
  51. typedef struct CH_DMA {
  52.   u32 src;                         /* $00 (SAR, source address)      */
  53.   u32 dst;                         /* $04 (DAR, destination address) */
  54.   u32 cnt;                         /* $08 (TCR, transfer count)      */
  55.   u32 ctrl;                        /* $0C (CHCR, control, i guess)   */
  56. } PACKED CH_DMA;
  57.  
  58. typedef enum dma_sizes {
  59.   DMA_SIZE_BYTE,                                  /* $01 byte.       */
  60.   DMA_SIZE_WORD,                                  /* $02 bytes.      */
  61.   DMA_SIZE_LONG,                                  /* $04 bytes.      */
  62.   DMA_SIZE_128B                                   /* $10 bytes!      */
  63. } dma_sizes;
  64.  
  65. // DMA channels, operation register, control registers
  66. #define DMA_REG ((volatile CH_DMA*)DMA_MEM)
  67. #define DMA_REG_OR ((volatile u32*)(0xFFFFFFB0))
  68. #define DMA_REG_CR ((volatile u8*)(0xFFFFFE71))
  69. // DMA destination is fixed, dest is incremented, dest is decremented
  70. // > used for changing the direction that the destination
  71. // > address goes during a transfer.
  72. #define DMA_DST_FIX (0<<14)
  73. #define DMA_DST_INC (1<<14)
  74. #define DMA_DST_DEC (2<<14)
  75. // DMA source fixed, src increments, src decrements
  76. // > same as the above, except with the source address.
  77. #define DMA_SRC_FIX (0<<12)
  78. #define DMA_SRC_INC (1<<12)
  79. #define DMA_SRC_DEC (2<<12)
  80. // DMA size
  81. // > controls the size of each unit transferred.
  82. // > $0 is 1 byte, $1 is 2 bytes, $2 is 4 bytes, $3 is 16 bytes.
  83. #define DMA_SIZE(n) (((n)&3)<<10)
  84.  
  85. // DMA auto-request, interrupt enable, transfer-end, enable
  86. #define DMA_AR (1<<9)
  87. #define DMA_IE (1<<2)
  88. #define DMA_TE (1<<1)
  89. #define DMA_ON (1)
  90.  
  91. // DMA master enable,NMIF,address error, priority
  92. #define DMA_DME (1)
  93. #define DMA_NMIF (1<<1)
  94. #define DMA_AE (1<<2)
  95. #define DMA_PR (1<<3)
  96.  
  97. // stop all DMA transfers
  98. INLINE void sh2_dma_stop()
  99. { *DMA_REG_OR &= (DMA_AE | DMA_PR | DMA_NMIF); }
  100. // initialize DMA channels
  101. INLINE void sh2_dma_init()
  102. {
  103.   sh2_dma_stop();
  104.   DMA_REG[0].ctrl = 0;
  105.   DMA_REG[1].ctrl = 0;
  106. }
  107. // check if DMA channel `ch` is active
  108. INLINE u32 sh2_dma_active(u32 ch)
  109. { return (!(DMA_REG[ch].ctrl&DMA_TE)) ? 1 : 0; }
  110. // blasts from `src` to `dst`, in `cnt` amount of transfers, using `mode`.
  111. INLINE void sh2_dma_blast(u32 ch, void *src,void *dst,u32 cnt,u32 mode)
  112. {
  113.   // "why are you using assembly?" it's easier to debug in an emu, trust me.
  114.   // alternatively, you may comment this part out and just use
  115.   // the C section (ha) below.
  116.   asm(
  117.     // move src,dst,cnt
  118.     "MOV.L %[src],@(0,%[ch])\t\n"
  119.     "MOV.L %[dst],@(4,%[ch])\t\n"
  120.     "MOV.L %[cnt],@(8,%[ch])\t\n"
  121.     // REG_CR[ch] = 0
  122.     "MOV #0,R0\t\n"
  123.     "MOV.B R0,@%[cr]\t\n"
  124.     // move ctrl to DMA_REG[ch].ctrl
  125.     "MOV.L @(12,%[ch]),R0\t\n" // read from ctrl before writing.
  126.     "MOV.L %[mode],@(12,%[ch])\t\n"
  127.     :: [ch]"r"(((u32)&DMA_REG[ch])),[src]"r"(src),
  128.     [dst]"r"(dst),[cnt]"r"(cnt),
  129.     [mode]"r"(mode),[cr]"r"(((u32)&DMA_REG_CR[ch]))
  130.   ); // */
  131.  
  132.   /* DMA_REG[ch].src = (u32)src;
  133.   DMA_REG[ch].dst = (u32)dst;
  134.   DMA_REG[ch].cnt = cnt;
  135.   DMA_REG_CR[ch] = 0; // external request
  136.   DMA_REG[ch].ctrl = (DMA_REG[ch].ctrl&0) | mode; // */
  137. }
  138.  
  139. /* DMA example: copy $10 bytes from WRAM_LO[$000000] to WRAM_LO[$000100]
  140.   * sh2_dma_init();
  141.   * DMA_REG_OR = DMA_DME | DMA_PR;
  142.   *
  143.   * sh2_dma_blast(0,
  144.   *   &WRAM_LO[0],&WRAM_LO[0x100],0x10,
  145.   *   DMA_SRC_INC|DMA_DST_INC|DMA_AR|DMA_ON
  146.   * );
  147.   * // DMA_SRC_INC is so the source address increases
  148.   * // DMA_DST_INC is so the destination address increases
  149.   * // DMA_AR is so it the transfer occurs immediately...?
  150.   ** idk what its actually for but if u dont put it in it doesn't copy
  151. */
  152.  
  153. /*---- CD defines ---------------------------------------------------*/
  154. // > NOTE: i have no clue on what the hell half of these registers do
  155. // > or what they're even for, just hope for the best.
  156. typedef struct CD_CR {
  157.   u16 dummy1, CR1;
  158.   u16 dummy2, CR2;
  159.   u16 dummy3, CR3;
  160.   u16 dummy4, CR4;
  161. } PACKED CD_CR;
  162.  
  163. #define CD_REG_BASE     (0x25890000)
  164. #define CD_REG_HIRQ     ((volatile u16*)(CD_REG_BASE + 0x0008))
  165. #define CD_REG_HIRQMASK ((volatile u16*)(CD_REG_BASE + 0x000C))
  166. #define CD_REG_CR       ((volatile CD_CR*)(CD_REG_BASE + 0x0018))
  167. #define CD_REG_MPEGRGB  ((volatile u16*)(CD_REG_BASE + 0x0028))
  168.  
  169. typedef struct
  170.  
  171. #endif
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