LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY c_sinc IS
    PORT (  CLK, r: IN STD_LOGIC;
        sr: out std_logic);
END c_sinc;

ARCHITECTURE comportamental OF c_sinc IS
    TYPE type_state IS (E0,E1,E2);
    SIGNAL Estado: type_state;
    SIGNAL Entradas: STD_LOGIC

BEGIN
    Entradas<= r;
    sr<='1'
    PROCESS (CLK)
    BEGIN

       IF (CLK'event and CLK='1') THEN

            CASE Estado IS

                WHEN E0 =>
                   if r='1' then Estado <= E0
                   elsif Entradas='0' then Estado <= E1; sr<=1;
                   end if;

                WHEN E1 =>

                    IF r='1' THEN Estado <= E0;
                    ELSIF Entradas= '0' THEN Estado <= E2;  sr<='0';
                    END IF;

                WHEN E2 =>

                    IF r='1' THEN Estado <= E0;
                    else r<='1';
                    END IF;


        END CASE;
        END IF;
    END PROCESS;
END comportamental;