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-- Company:
-- Engineer:
--
-- Create Date:    08:51:26 05/21/2018
-- Design Name:
-- Module Name:    counter_1k_dec - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.STD_LOGIC_UNSIGNED.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rand_dec is
    Port (  clk   : in  STD_LOGIC;
            rand  : out  STD_LOGIC_VECTOR (15 downto 0));
end rand_dec;

architecture Behavioral of rand_dec is

signal d2, d3, d4 : std_logic_vector(3 downto 0) := "0000";
signal d1 : std_logic := "0001";
signal bin_c : std_logic_vector(15 downto 0) := "0000000000000000";

begin

dec <= d1 & d2 & d3 & d4;
bin <= bin_c;

process(clk)

begin

    if falling_edge(clk) then

        d4 <= d4 + 1;
        if d4 = 9 then
            d4 <= "0000";
            d3 <= d3 + 1;
            if d3 = 9 then
                d3 <= "0000";
                d2 <= d2 + 1;
                if d2 = 9 then
                    d2 <= "0000";
                    d1 <= d1 + 1;
                    if d1 = 9 then
                        d1 <= "0001";

                    end if;
                end if;
            end if;
        end if;

    end if;
end process;
end Behavioral;