----------------------------------------------------------------------------------
-- Company:
-- Engineer: Nabil Sayegh
--
-- Create Date:    12:11:03 08/07/2009
-- Design Name:
-- Module Name:    fifo_fwft - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

entity fifo_fwft is
    generic
    (
    addr_width : Integer;
    data_width : Integer
    );
    port
    (
        clock              : IN  std_logic;
        reset              : IN  std_logic;

        wren               : IN  std_logic;
        rdack              : IN  std_logic;
        din                : IN  std_logic_vector(data_width-1 downto 0);
        dout               : OUT std_logic_vector(data_width-1 downto 0);
        valid              : OUT std_logic;
        almost_full        : OUT std_logic
    );
end entity fifo_fwft;

architecture Behavioral of fifo_fwft is
    signal rden : std_logic;
    signal valid_reg : std_logic;

    signal empty : std_logic;
begin

    Inst_fifo: entity work.fifo_simple
    generic MAP
    (
        addr_width => addr_width,
        data_width => data_width
    )
    port map
    (
        clock => clock,
        reset => reset,
        wren => wren,
        rden => rden,
        din => din,
        dout => dout,
        empty => empty,
        almost_full => almost_full
    );

    -- fwft fifo replaces empty by a valid signal
    -- if we ack a read, then the next data will be at the output in the next cycle and valid still high
    -- otherwise, if there is no data anymore, valid will be 0 at the next cycle


    -- if current data isn't valid anymore and there is more data -> prefetch
    rden <= (not valid_reg and not empty) or (rdack and not empty);
    valid <= valid_reg;
--  assert not (valid_reg='0' and rdack='1') report "Usage error! valid='0' and rdack='1' is forbidden: " & integer'image(to_integer(unsigned'(0=>valid_reg))) & "/" & integer'image(to_integer(unsigned'(0=>rdack)));
    process (clock, reset)
    begin
        if rising_edge(clock) then
            -- look ahead
            -- if previously the data was valid and it wasn't read or there is even more data
            -- the second part can be seen as a delayed empty

            valid_reg <= (valid_reg and not rdack) or (not empty);

        end if;

        if reset = '1' then
            valid_reg <= '0';
        end if;
    end process;

end architecture Behavioral;