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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 09:55:25 11/21/2014
- -- Design Name:
- -- Module Name: Counter - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use ieee.std_logic_unsigned.all;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity VGADriver is
- Port ( Reset : in STD_LOGIC;
- CLK50 : in STD_LOGIC;
- P1, P2 : in STD_LOGIC;
- R, G, B, Hsync, Vsync : out STD_LOGIC);
- end VGADriver;
- architecture Behavioral of VGADriver is
- signal Add1, Add2 : STD_LOGIC_VECTOR(9 downto 0);
- signal Reg1, Reg2 : STD_LOGIC_VECTOR(9 downto 0);
- signal Mux1, Mux2 : STD_LOGIC_VECTOR(9 downto 0);
- signal Cmp1, Cmp2 : STD_LOGIC;
- signal Rows : STD_LOGIC_VECTOR(9 downto 0) := "1100100000";
- signal Columns : STD_LOGIC_VECTOR(9 downto 0) := "1000001001";
- signal CLK : STD_LOGIC;
- ----------- PLAYER -----------------
- signal PosX, RegX : STD_LOGIC_VECTOR(9 downto 0) := "0010010000";
- signal PosY, RegY : STD_LOGIC_VECTOR(9 downto 0) := "0000100000";
- signal AddX, SubX : STD_LOGIC_VECTOR(9 downto 0);
- signal AddY, SubY : STD_LOGIC_VECTOR(9 downto 0);
- ----------- PLAYER 2 -----------------
- signal Pos2X, Reg2X : STD_LOGIC_VECTOR(9 downto 0) := "1100000000";
- signal Pos2Y, Reg2Y : STD_LOGIC_VECTOR(9 downto 0) := "0000100000";
- signal Add2X, Sub2X : STD_LOGIC_VECTOR(9 downto 0);
- signal Add2Y, Sub2Y : STD_LOGIC_VECTOR(9 downto 0);
- ----------- SCORES --------------------
- signal Score1, Score2 : STD_LOGIC_VECTOR(6 downto 0) := "1111111";
- signal RegS1, RegS2 : STD_LOGIC_VECTOR(6 downto 0) := "1111111";
- signal SubS1, SubS2 : STD_LOGIC_VECTOR(6 downto 0);
- ----------- BOT ---------------------
- signal BPosX, BRegX : STD_LOGIC_VECTOR(9 downto 0) := "0100000000";
- signal BPosY, BRegY : STD_LOGIC_VECTOR(9 downto 0) := "0010000000";
- signal BAddX, BSubX : STD_LOGIC_VECTOR(9 downto 0);
- signal BAddY, BSubY : STD_LOGIC_VECTOR(9 downto 0);
- signal BRightReg, BDownReg : STD_LOGIC := '1';
- signal BRightMux, BDownMux : STD_LOGIC;
- ----------- TIMER ------------------
- signal TimerReg, TimerAdd, TimerMux : STD_LOGIC_VECTOR(25 downto 0);
- signal TimerCmp, TimerCmpBot : STD_LOGIC;
- begin
- --posX <= posX + 1 when Right = '1' else posX - 1 when Left = '1';
- --posY <= posY + 1 when Down = '1' else posY - 1 when Up = '1';
- CLK <= not(CLK) when rising_edge(CLK50);
- Hsync <= '0' when 0 <= Reg1 and Reg1 < 96 else '1';
- Vsync <= '0' when 0 <= Reg2 and Reg2 < 2 else '1';
- R <= '0' when (0 <= Reg1 and Reg1 < 144) OR (144+640 <= Reg1 and Reg1 < 144+640+16) OR (0 <= Reg2 and Reg2 < 31) OR (31+480 <= Reg2 and Reg2 < 31+480+10) else
- '1' when ((Pos2X <= Reg1 and Reg1 < Pos2X+16) and (Pos2Y <= Reg2 and Reg2 < Pos2Y+64)) or ((Reg1 > 464 and Reg1 < 464 + Score2) and (Reg2 > 489 and Reg2 < 505)) else
- '0';
- G <= '0' when (0 <= Reg1 and Reg1 < 144) OR (144+640 <= Reg1 and Reg1 < 144+640+16) OR (0 <= Reg2 and Reg2 < 31) OR (31+480 <= Reg2 and Reg2 < 31+480+10) else
- '1' when (BPosX <= Reg1 and Reg1 < BPosX+16) and (BPosY <= Reg2 and Reg2 < BPosY+16) else
- '0';
- B <= '0' when (0 <= Reg1 and Reg1 < 144) OR (144+640 <= Reg1 and Reg1 < 144+640+16) OR (0 <= Reg2 and Reg2 < 31) OR (31+480 <= Reg2 and Reg2 < 31+480+10) else
- '1' when (PosX <= Reg1 and Reg1 < PosX+16) and (PosY <= Reg2 and Reg2 < PosY+64) else
- '0';
- ----------------------------------------
- Add1 <= Reg1 + "0000000001";
- Mux1 <= Add1 when Cmp1 = '0' else "0000000000" when Cmp1 = '1';
- Cmp1 <= '1' when Add1 > Rows else '0';
- Reg1 <= "0000000000" when Reset = '0' else Mux1 when rising_edge(CLK);
- -----------------------------------------
- Add2 <= Reg2 + "0000000001";
- Mux2 <= "0000000000" when Cmp2 = '1' and Cmp1='1' else
- Add2 when Cmp2 = '0' and Cmp1 = '1' else
- Reg2;
- Cmp2 <= '1' when Add2 > Columns else '0';
- Reg2 <= "0000000000" when Reset = '0' else Mux2 when rising_edge(CLK);
- -----------------------------------------
- -- Timer
- TimerAdd <= TimerReg + "00000000000000000000000001";
- TimerReg <= TimerMux when rising_edge(CLK);
- TimerMux <= "00000000000000000000000000" when TimerCmp = '1' else
- TimerAdd ;
- TimerCmp <= '1' when TimerAdd > "00000000111010000100100000" else '0';
- TimerCmpBot <= '1' when TimerAdd > "00000001011010000100100000" else '0';
- -----------------------------------------
- -- PosX
- --RegX <= PosX when rising_edge(CLK) ;
- --AddX <= RegX + "0000000001";
- --SubX <= RegX - "0000000001";
- --PosX <= AddX when (Right = '1' and TimerCmp = '1' and RegX < "1100000000") else
- -- SubX when (Right = '0' and TimerCmp = '1' and RegX > "0010010000") else
- -- "0010010000" when Reset = '0' else
- -- RegX;
- -----------------------------------------
- -- PLAYER 1 - PosY
- RegY <= PosY when rising_edge(CLK) ;
- AddY <= RegY + "0000000011";
- SubY <= RegY - "0000000011";
- PosY <= AddY when (P1 = '1' and TimerCmp = '1' and RegY < 457) else
- SubY when (P1 = '0' and TimerCmp = '1' and RegY > 31) else
- "0010010000" when Reset = '0' else
- RegY;
- -----------------------------------------
- -- PLAYER 2 - PosY
- Reg2Y <= Pos2Y when rising_edge(CLK) ;
- Add2Y <= Reg2Y + "0000000011";
- Sub2Y <= Reg2Y - "0000000011";
- Pos2Y <= Add2Y when (P2 = '1' and TimerCmp = '1' and Reg2Y < 457) else
- Sub2Y when (P2 = '0' and TimerCmp = '1' and Reg2Y > 31) else
- "0010010000" when Reset = '0' else
- Reg2Y;
- ------------------------------------------
- -- Bot X
- BRegX <= BPosX when rising_edge(CLK);
- BAddX <= BRegX + "0000000011";
- BSubX <= BRegX - "0000000011";
- BPosX <= BAddX when (BRightMux = '1' and TimerCmp = '1') else
- BSubX when (BRightMux = '0' and TimerCmp = '1') else
- "0100000000" when Reset = '0' else
- BRegX;
- BRightReg <= BRightMux when rising_edge(CLK);
- BRightMux <= '1' when (BRightReg = '0' and (BRegX < "0010010000" or (BRegX < RegX+16 and (BRegY<RegY+64 and BRegY>RegY)))) else --( (BRegX < RegX+16 and (BRegY<RegY+64 or BRegY>RegY)))) else
- '0' when (BRightReg = '1' and (BRegX > "1100000000" or (BRegX+16 > Reg2X and (BRegY<Reg2Y+64 and BRegY>Reg2Y)))) else-- ) else --or (BRegX+16 > RegX and (BRegY<RegY+64 or BRegY+64>RegY)))) else
- BRightReg;
- -----------------------------------------
- -- Bot Y
- BRegY <= BPosY when rising_edge(CLK);
- BAddY <= BRegY + "0000000011";
- BSubY <= BRegY - "0000000011";
- BPosY <= BAddY when (BDownMux = '1' and TimerCmp = '1') else
- BSubY when (BDownMux = '0' and TimerCmp = '1') else
- "0010000000" when Reset = '0' else
- BRegY;
- BDownReg <= BDownMux when rising_edge(CLK);
- BDownMux <= '1' when (BDownReg = '0' and BRegY < 31) else --or (BRegY < RegY+16 and (BRegX<RegX+16 or BRegX+16>RegX) ))
- '0' when (BDownReg = '1' and BRegY > 473) else --or (BRegY+16 > RegY and (BRegX<RegX+16 or BRegX+16>RegX) )) ) else
- BDownReg;
- -----------------------------------------
- -- Score 1
- RegS1 <= Score1 when rising_edge(CLK);
- SubS1 <= RegS1 - "0001000";
- Score1 <= SubS1 when BRegX > "1100000000" else RegS1;
- -----------------------------------------
- -- Score 2
- RegS2 <= Score2 when rising_edge(CLK);
- SubS2 <= RegS2 - "0001000";
- Score2 <= SubS2 when BRegX < "0010010000" else RegS2;
- end Behavioral;
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