library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;

entity mux2 is


    port
    (
        -- Input ports
        hex1    : out  std_logic_vector(6 downto 0);
        hex10   : out std_logic_vector(6 downto 0);
        player: in std_logic


    );
end mux2;




architecture mux2_impl of mux2 is
signal  a1  :  std_logic_vector(6 downto 0);
signal  a10 :  std_logic_vector(6 downto 0);
signal  b1 :  std_logic_vector(6 downto 0);
signal  b10 :  std_logic_vector(6 downto 0);

begin

    aa: entity guess_game port map(
        seg1=>a1,
        seg10=>a10);

    bb: entity guess_game port map(
        seg1=>b1,
        seg10=>b10);

    process(player,a1,a10,b1,b10) is
        begin
        if player = "1" then
            hex1 <= a1;
            hex10 <=a10;
        else
            hex1 <= b1;
            hex10 <= b10;
        end if;
    end process;


end mux2_impl;