LucaSkywalker

Counter3.vhd

Oct 31st, 2020
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  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use IEEE.std_logic_arith.all;
  4. use IEEE.std_logic_misc.all;
  5. use IEEE.std_logic_unsigned.all;
  6.  
  7. entity Counter3 is
  8.     Port (  Input:  IN      STD_LOGIC;
  9.             Clk:    IN      STD_LOGIC;
  10.             Rst:    IN      STD_LOGIC;
  11.             Output: OUT     STD_LOGIC);
  12. end Counter3;
  13.  
  14. architecture Behavioral of Counter3 is
  15.     begin
  16.     Main: process(Clk, Rst)
  17.     variable count : STD_LOGIC_VECTOR(1 DOWNTO 0);
  18.     variable last : STD_LOGIC;
  19.         begin
  20.         if Rst = '1' then
  21.                 count := "00";
  22.                 last := '0';
  23.                 Output <= '0';
  24.         elsif Rising_Edge(CLK) then
  25.             if count = "11" then
  26.                 Output <= '0';
  27.                 count := "00";
  28.             elsif input = '0' then
  29.                 if last = '0' then
  30.                     count := "00";
  31.                     Output <= '0';
  32.                 end if;
  33.             elsif input = '1' then
  34.                 if count = "10" then
  35.                     Output <= '1';
  36.                     count := count + 1;
  37.                 else
  38.                     count := count + 1;
  39.                     Output <= '0';
  40.                 end if;
  41.             end if;
  42.         last := input;
  43.         end if;
  44.     end process Main;
  45. end Behavioral;
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