----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    11:49:43 05/21/2019
-- Design Name:
-- Module Name:    demux1na4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity demux1na4 is
    Port ( wyjscie : out  STD_LOGIC_VECTOR (3 downto 0);
           wejscie : in  STD_LOGIC_VECTOR (1 downto 0));
end demux1na4;

architecture Behavioral of demux1na4 is

begin

with wejscie select
    wyjscie <=  "1110" when "00",
                    "1101" when "01",
                    "1011" when "10",
                    "0111" when others;


end Behavioral;