mee_moo

------ mee_moo ------
library ieee;
use ieee.std_logic_1164.all;

entity mee_moo is
port(
    clk     : in std_logic;
    reset   : in std_logic;
    inp     : in std_logic_vector(1 downto 0);
    moo_out : out std_logic;
    mee_out : out std_logic);
end mee_moo;

architecture state_machine of mee_moo is
    type    state is(idle, init, aktiv);
    signal  present_state, next_state : state;
begin

    state_reg: process(clk, reset)  -- state register instantieres
    begin
        if reset = '0' then             -- reset af state machine
            present_state <= idle;
        elsif rising_edge(clk) then     -- næste state ved rising_edge af clk
            present_state <= next_state;
        end if;
    end process;

    next_st: process(inp, present_state)
    begin
    next_state <= present_state;        -- states defineres ud fra ibd
        case present_state is
            when idle =>
                if (inp = "10" or inp = "11") then
                    next_state <= init;
                end if;
            when init =>
                if (inp = "00") then
                    next_state <= idle;
                elsif (inp = "01") then
                    next_state <= aktiv;
                end if;
            when aktiv =>
                next_state <= idle;
        end case;
    end process;

    moo_output: process(present_state)  -- output for moo defineres ift. ibd
    begin
        case present_state is
            when idle =>
                moo_out <= '0';
            when others =>
                moo_out <= '1';
        end case;
    end process;

    mee_output: process(present_state, inp) -- output for mee defineres ift. ibd
    begin
        case present_state is
            when init =>
                if (inp = "11") then
                    mee_out <= '1';
                else
                    mee_out <= '0';
                end if;
            when others =>
                mee_out <= '0';
        end case;
    end process;

end state_machine;