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somador vetor

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Jul 16th, 2018
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VHDL 0.50 KB | None | 0 0
  1. -- Somador 2 bits (com vetores)
  2. -- Portas: Entradas: in_a (vetor 2 posições), in_b (vetor 2 posições) / Saídas: out_soma (vetor 3 posições)
  3. -- Autores: João Vitor e Marcos Meira
  4.  
  5. library IEEE;
  6. use IEEE.STD_LOGIC_1164.ALL;
  7. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  8.  
  9. entity sum_2bits is
  10.     port (in_a, in_b: in std_logic_vector (1 downto 0);
  11.           out_soma: out std_logic_vector (2 downto 0));
  12. end sum_2bits;
  13.  
  14. architecture dataflow of sum_2bits is
  15. begin
  16. out_soma <= ('0' & in_a) + ('0' & in_b);
  17. end dataflow;
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