read_verilog f16_dec_comb.v

read_verilog -lib +/ice40/cells_sim.v
hierarchy -check -top top
proc

flatten
tribuf -logic
deminout

opt_expr
opt_clean
check
opt
wreduce
share
techmap -map +/cmp2lut.v -D LUT_WIDTH=4
opt_expr
opt_clean
alumacc
opt
fsm
opt -fast
memory -nomap
opt_clean

opt -fast -mux_undef -undriven -fine
memory_map
opt -undriven -fine

simplemap
flowmap -maxlut 4

techmap -map +/techmap.v -map +/ice40/arith_map.v
ice40_opt

dffsr2dff
dff2dffe -direct-match $_DFF_*
techmap -D NO_LUT -map +/ice40/cells_map.v
opt_expr -mux_undef
simplemap
ice40_ffinit
ice40_ffssr
ice40_opt -full

techmap -map +/ice40/latches_map.v
abc -dress -lut 4
clean
ice40_unlut
opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3

techmap -map +/ice40/cells_map.v
clean

hierarchy -check
stat
check -noinit

write_json test.json