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Feb 22nd, 2019
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  1. read_verilog f16_dec_comb.v
  2.  
  3. read_verilog -lib +/ice40/cells_sim.v
  4. hierarchy -check -top top
  5. proc
  6.  
  7. flatten
  8. tribuf -logic
  9. deminout
  10.  
  11. opt_expr
  12. opt_clean
  13. check
  14. opt
  15. wreduce
  16. share
  17. techmap -map +/cmp2lut.v -D LUT_WIDTH=4
  18. opt_expr
  19. opt_clean
  20. alumacc
  21. opt
  22. fsm
  23. opt -fast
  24. memory -nomap
  25. opt_clean
  26.  
  27. opt -fast -mux_undef -undriven -fine
  28. memory_map
  29. opt -undriven -fine
  30.  
  31. simplemap
  32. flowmap -maxlut 4
  33.  
  34. techmap -map +/techmap.v -map +/ice40/arith_map.v
  35. ice40_opt
  36.  
  37. dffsr2dff
  38. dff2dffe -direct-match $_DFF_*
  39. techmap -D NO_LUT -map +/ice40/cells_map.v
  40. opt_expr -mux_undef
  41. simplemap
  42. ice40_ffinit
  43. ice40_ffssr
  44. ice40_opt -full
  45.  
  46. techmap -map +/ice40/latches_map.v
  47. abc -dress -lut 4
  48. clean
  49. ice40_unlut
  50. opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
  51.  
  52. techmap -map +/ice40/cells_map.v
  53. clean
  54.  
  55. hierarchy -check
  56. stat
  57. check -noinit
  58.  
  59. write_json test.json
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