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ckroy

Untitled

Mar 27th, 2021
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  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use IEEE.numeric_std.all;
  4. USE IEEE.std_logic_arith.all;
  5. USE IEEE.std_logic_unsigned.all;
  6.  
  7. entity assingment is
  8.   Port ( A : in std_logic_vector (3 downto 0);
  9.  B : in std_logic_vector (3 downto 0);
  10.  Y : out std_logic_vector (3 downto 0);
  11.  sel : in std_logic_vector (3 downto 0);
  12.  Flag : out std_logic) ;
  13. end entity;
  14.  
  15. architecture Behavioral of assingment is
  16. signal Comp : std_logic_vector (3 downto 0);
  17. signal tmp: std_logic_vector (4 downto 0);
  18.  
  19. begin
  20. process(A, B, sel) is
  21. begin
  22. case sel is
  23.  when "0000" => Y <= A;
  24.  when "0001" => Y <= B;
  25.  when "0011" => Y <= A or B; -- OR Gate
  26.  when "0101" => Y <= A nor B; -- NOR Gate
  27.  when "0110" => Y <= A xor B; -- XOR Gate
  28.  when "0111" => Y <= A xnor B; -- XNOR Gate
  29.  
  30.  if(A>B) then
  31.     Comp <= x"1" ;
  32.    else
  33.     Comp <= x"0" ;
  34.    end if;
  35.  
  36.  when others => Y <= x"0";
  37.  tmp <= ('0' & A) + ('0' & B);
  38.  Flag <= tmp(4); -- flag
  39.  
  40. end case;
  41.  
  42. end process;
  43. end architecture;
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