library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

entity assingment is
  Port ( A : in std_logic_vector (3 downto 0);
 B : in std_logic_vector (3 downto 0);
 Y : out std_logic_vector (3 downto 0);
 sel : in std_logic_vector (3 downto 0);
 Flag : out std_logic) ;
end entity;

architecture Behavioral of assingment is
signal Comp : std_logic_vector (3 downto 0);
signal tmp: std_logic_vector (4 downto 0);

begin
process(A, B, sel) is
begin
case sel is
 when "0000" => Y <= A;
 when "0001" => Y <= B;
 when "0011" => Y <= A or B; -- OR Gate
 when "0101" => Y <= A nor B; -- NOR Gate
 when "0110" => Y <= A xor B; -- XOR Gate
 when "0111" => Y <= A xnor B; -- XNOR Gate

 if(A>B) then
    Comp <= x"1" ;
   else
    Comp <= x"0" ;
   end if;

 when others => Y <= x"0";
 tmp <= ('0' & A) + ('0' & B);
 Flag <= tmp(4); -- flag

end case;

end process;
end architecture;