Muxdos

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-- Company:
-- Engineer:
--
-- Create Date: 03.09.2021 11:05:43
-- Design Name:
-- Module Name: MUXdos - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MUXdos is
--  Port ( );
Port(
    a: in std_logic_vector(15 downto 0);
    b: in std_logic_vector(15 downto 0);
    Selector: in std_logic;
    Salida: out std_logic_vector(15 downto 0)
);
end MUXdos;

architecture Behavioral of MUXdos is

begin
process(a,b,Selector)
begin
    if Selector = '0'
        then
          Salida <= a;
    elsif Selector = '1'
         then
            Salida <= b;
    end if;
end process;

end Behavioral;