one_digit_clock_tester

--------- one_digit_clock_tester ---------
Library ieee;
use ieee.std_logic_1164.all;

entity one_digit_clock_tester is
port(
    KEY         : in std_logic_vector(3 downto 0);
    CLOCK_50    : in std_logic;
    SW          : in std_logic_vector(17 downto 16);
    HEX0        : out std_logic_vector(6 downto 0);
    LEDR        : out std_logic_vector(0 downto 0));
end one_digit_clock_tester;

architecture structural of one_digit_clock_tester is
    signal countBin     : std_logic_vector(3 downto 0);
    signal clkOut       : std_logic;
begin

I1: entity work.clock_gen
     port map(
        clk     => CLOCK_50,
        reset   => KEY(3),
        speed   => KEY(0),
        clk_out => clkOut);

I2: entity work.multi_counter
     port map(
        CLK     => clkOut,
        reset   => KEY(3),
        mode    => SW,
        count   => countBin,
        cout    => LEDR);

I3: entity work.bin2hex
     port map(
        bin     => countBin,
        seg     => HEX0);

end structural;