even bits detector

library ieee;
use ieee.std_logic_1164.all;

entity even_bits_detector is
    port( X: in STD_Logic;
        clk: in STD_Logic;
        Z: out STD_Logic);
end even_bits_detector;
architecture behavior of even_bits_detector is
TYPE State_Type is (A,B,C,D,E,F,G,H,I);
SIGNAL state: State_Type;
begin
    process(clk)
    begin
        if rising_edge(clk) then
            case state is
                when A =>
                    if X = '0' then
                        Z <= '0';
                        state <= B;
                    else
                        Z <= '0';
                        state <= C;
                    end if;
                when B =>
                    if X = '0' then
                        Z <= '1';
                        state <= D;
                    else
                        Z <= '0';
                        state <= E;
                    end if;
                when C =>
                    if X = '0' then
                        Z <= '0';
                        state <= E;
                    else
                        Z <= '1';
                        state <= F;
                    end if;
                when D =>
                    if X = '0' then
                        Z <= '0';
                        state <= B;
                    else
                        Z <= '1';
                        state <= C;
                    end if;
                when E =>
                    if X = '0' then
                        Z <= '1';
                        state <= G;
                    else
                        Z <= '1';
                        state <= H;
                    end if;
                when F =>
                    if X = '0' then
                        Z <= '1';
                        state <= B;
                    else
                        Z <= '0';
                        state <= C;
                    end if;
                when G =>
                    if X = '0' then
                        Z <= '0';
                        state <= E;
                    else
                        Z <= '1';
                        state <= I;
                    end if;
                when H =>
                    if X = '0' then
                        Z <= '1';
                        state <= I;
                    else
                        Z <= '0';
                        state <= E;
                    end if;
                when I =>
                    if X = '0' then
                        Z <= '1';
                        state <= B;
                    else
                        Z <= '1`';
                        state <= C;
                    end if;
                when others =>
                    state <= A;
            end case;
        end if;
    end process;
end behavior;