add_sub.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity add_sub is
    port(
        a        : in  std_logic_vector(31 downto 0);
        b        : in  std_logic_vector(31 downto 0);
        sub_mode : in  std_logic;
        carry    : out std_logic;
        zero     : out std_logic;
        r        : out std_logic_vector(31 downto 0)
    );
end add_sub;

architecture synth of add_sub is
    signal b_result: std_logic_vector(32 downto 0);
    signal r_result: std_logic_vector(32 downto 0);
begin

    b_result<= ('0' & b) xor (32 downto 0 => sub_mode);

    r_result<= std_logic_vector(signed(b_result)+signed('0'&a)); -- leading bits extension ?

    carry<=r_result(32);

    assign_r: process(r_result)
        begin
            r<=r_result(31 downto 0);
        end process assign_r;

    check_zero: process(r_result)
    begin
        if(r_result = (r_result'range => '0')) then
            zero<='1';
        else
            zero<='0';
        end if;
    end process check_zero;

end synth;