FSM_Moore

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity simple is
port (
    clock, reset, w :   in std_logic;
    z:                  out std_logic
);

end simple;

architecture comp of simple is
    type statetype is (A, B, C);

    signal y: statetype;

begin
    process (clock, reset) begin
      if reset = '0' then y <= A;
          elsif (clock'event and clock = '1') then
          case y is
              when A =>
                  if (w = '0')
                      then y <= A;
                      else y <= B;
                  end if;
              when B =>
                  if (w = '0')
                      then y <= A;
                      else y <= C;
                  end if;
              when C =>
                  if (w = '0')
                      then y <= A;
                      else y <= C;
                  end if;
           end case;
       end if;
     end process;
    z <= '1' when y = C else '0';
end comp;