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- library IEEE; -- zmienić na i := '0' warunek początkowy w sterowaniu
- use IEEE.STD_LOGIC_1164.ALL;
- entity Stoper is
- Port ( rst_i : in STD_LOGIC;
- clk_i : in STD_LOGIC; -- 50 MHz
- start_stop_button_i : in STD_LOGIC := '0';
- an_o : out STD_LOGIC_VECTOR (3 downto 0);
- seg_o : out STD_LOGIC_VECTOR (7 downto 0));
- end Stoper;
- architecture Behavioral of Stoper is
- signal cyferki : STD_LOGIC_VECTOR (31 downto 0); -- bez kropek
- -- signal wlacznik : STD_LOGIC := '0';
- signal CLK_dziel : STD_LOGIC;
- signal BTN_stabilny : STD_LOGIC := '0';
- signal BTN_zbocze_nar : STD_LOGIC := '0';
- signal i : integer range 0 to 3 := 0;
- signal ms1 : integer range 0 to 10000 := 0;
- signal ms10 : integer range 0 to 10 := 0;
- signal ms100 : integer range 0 to 10 := 0;
- signal ms1000 : integer range 0 to 10 := 0;
- signal ms10000 : integer range 0 to 10 := 0;
- component dzielnik_czt
- port ( CLK_i : in STD_LOGIC;
- RST_i : in STD_LOGIC;
- led7 : out STD_LOGIC
- );
- end component;
- component eliminator_drg
- port ( CLK_i : in STD_LOGIC;
- guzik_drg : in STD_LOGIC;
- guzik_stab : out STD_LOGIC
- );
- end component;
- component wykr_zbocza
- port ( CLK_i : in STD_LOGIC;
- sygn_wej : in STD_LOGIC;
- zbocze : out STD_LOGIC
- );
- end component;
- component sterowanie
- port ( CLK_i : in STD_LOGIC;
- RST_i : in STD_LOGIC;
- AN : out STD_LOGIC_vector (3 downto 0)
- );
- end component;
- function Dekoder (arg: integer) return STD_LOGIC_VECTOR is
- begin
- case arg is
- when 0 => return "0000001"; --0
- when 1 => return "1001111"; --1
- when 2 => return "0010010"; --2
- when 3 => return "0000110"; --3
- when 4 => return "1001100"; --4
- when 5 => return "0100100"; --5
- when 6 => return "0100000"; --6
- when 7 => return "0001111"; --7
- when 8 => return "0000000"; --8
- when 9 => return "0000100"; --9
- when others => return "1111110"; -- "-"
- end case;
- end function Dekoder;
- begin
- CMP1: dzielnik_czt port map(
- CLK_i => clk_i,
- RST_i => rst_i,
- led7 => CLK_dziel);
- CMP2: eliminator_drg port map(
- CLK_i => clk_i,
- guzik_drg => start_stop_button_i,
- guzik_stab => BTN_stabilny);
- CMP3: wykr_zbocza port map(
- CLK_i => clk_i,
- sygn_wej => BTN_stabilny,
- zbocze => BTN_zbocze_nar);
- CMP4: sterowanie port map(
- CLK_i => clk_i,
- RST_i => rst_i,
- AN => an_o);
- -- Start_stop : process (CLK_i) is
- -- begin
- -- if rising_edge(CLK_i) then
- -- if (BTN_zbocze_nar = '1') then
- -- wlacznik <= not(wlacznik);
- -- end if;
- -- end if;
- -- end process Start_stop;
- Dzialanie : process (CLK_i, CLK_dziel, RST_i) is
- variable wlacznik : STD_LOGIC := '0';
- begin
- if rising_edge(CLK_i) then
- if (BTN_zbocze_nar = '1') then
- wlacznik := not(wlacznik);
- end if;
- end if;
- if (RST_i = '1') then
- ms1 <= 0;
- ms10 <= 0;
- ms100 <= 0;
- ms1000 <= 0;
- ms10000 <= 0;
- wlacznik := '0';
- elsif rising_edge(CLK_dziel) then
- if (wlacznik = '1') then
- ms1 <= ms1 + 1;
- if (ms1 = 10) then ms10 <= ms10 + 1; ms1 <= 0; end if;
- if (ms10 = 10) then ms100 <= ms100 + 1; ms10 <= 0; end if;
- if (ms100 = 10) then ms1000 <= ms1000 + 1; ms100 <= 0; end if;
- if (ms1000 = 10) then ms10000 <= ms10000 + 1; ms1000 <= 0; end if;
- if ms10000 > 5 then
- ms10 <= 10;
- ms100 <= 10;
- ms1000 <= 10;
- ms10000 <= 10;
- end if;
- end if;
- case i is
- when 3 => seg_o <= cyferki(31 downto 24); i <= i - 1;
- when 2 => seg_o <= cyferki(23 downto 16); i <= i - 1;
- when 1 => seg_o <= cyferki(15 downto 8); i <= i - 1;
- when 0 => seg_o <= cyferki(7 downto 0); i <= 3;
- end case;
- end if;
- end process Dzialanie;
- cyferki(31 downto 25) <= Dekoder(ms10000);
- cyferki(23 downto 17) <= Dekoder(ms1000);
- cyferki(15 downto 9) <= Dekoder(ms100);
- cyferki(7 downto 1) <= Dekoder(ms10);
- cyferki(0) <= '1';
- cyferki(8) <= '1';
- cyferki(16) <= '0';
- cyferki(24) <= '1';
- end Behavioral;
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