API tools faq
paste
Advertisement
Guest User

core_cmFunc.h

a guest
Jan 6th, 2018
369
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
C 15.18 KB | None | 0 0
raw download clone embed print report
  1. /**************************************************************************//**
  2.  * @file     core_cmFunc.h
  3.  * @brief    CMSIS Cortex-M Core Function Access Header File
  4.  * @version  V2.10
  5.  * @date     26. July 2011
  6.  *
  7.  * @note
  8.  * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  9.  *
  10.  * @par
  11.  * ARM Limited (ARM) is supplying this software for use with Cortex-M
  12.  * processor based microcontrollers.  This file can be freely distributed
  13.  * within development tools that are supporting such ARM based processors.
  14.  *
  15.  * @par
  16.  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  17.  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  18.  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  19.  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  20.  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  21.  *
  22.  ******************************************************************************/
  23.  
  24. #ifndef __CORE_CMFUNC_H
  25. #define __CORE_CMFUNC_H
  26.  
  27.  
  28. /* ###########################  Core Function Access  ########################### */
  29. /** \ingroup  CMSIS_Core_FunctionInterface  
  30.     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  31.   @{
  32.  */
  33.  
  34. #if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
  35. /* ARM armcc specific functions */
  36.  
  37. #if (__ARMCC_VERSION < 400677)
  38.   #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
  39. #endif
  40.  
  41. /* intrinsic void __enable_irq();     */
  42. /* intrinsic void __disable_irq();    */
  43.  
  44. /** \brief  Get Control Register
  45.     This function returns the content of the Control Register.
  46.     \return               Control Register value
  47.  */
  48. static __INLINE uint32_t __get_CONTROL(void)
  49. {
  50.   register uint32_t __regControl         __ASM("control");
  51.   return(__regControl);
  52. }
  53.  
  54.  
  55. /** \brief  Set Control Register
  56.     This function writes the given value to the Control Register.
  57.     \param [in]    control  Control Register value to set
  58.  */
  59. static __INLINE void __set_CONTROL(uint32_t control)
  60. {
  61.   register uint32_t __regControl         __ASM("control");
  62.   __regControl = control;
  63. }
  64.  
  65.  
  66. /** \brief  Get ISPR Register
  67.     This function returns the content of the ISPR Register.
  68.     \return               ISPR Register value
  69.  */
  70. static __INLINE uint32_t __get_IPSR(void)
  71. {
  72.   register uint32_t __regIPSR          __ASM("ipsr");
  73.   return(__regIPSR);
  74. }
  75.  
  76.  
  77. /** \brief  Get APSR Register
  78.     This function returns the content of the APSR Register.
  79.     \return               APSR Register value
  80.  */
  81. static __INLINE uint32_t __get_APSR(void)
  82. {
  83.   register uint32_t __regAPSR          __ASM("apsr");
  84.   return(__regAPSR);
  85. }
  86.  
  87.  
  88. /** \brief  Get xPSR Register
  89.     This function returns the content of the xPSR Register.
  90.     \return               xPSR Register value
  91.  */
  92. static __INLINE uint32_t __get_xPSR(void)
  93. {
  94.   register uint32_t __regXPSR          __ASM("xpsr");
  95.   return(__regXPSR);
  96. }
  97.  
  98.  
  99. /** \brief  Get Process Stack Pointer
  100.     This function returns the current value of the Process Stack Pointer (PSP).
  101.     \return               PSP Register value
  102.  */
  103. static __INLINE uint32_t __get_PSP(void)
  104. {
  105.   register uint32_t __regProcessStackPointer  __ASM("psp");
  106.   return(__regProcessStackPointer);
  107. }
  108.  
  109.  
  110. /** \brief  Set Process Stack Pointer
  111.     This function assigns the given value to the Process Stack Pointer (PSP).
  112.     \param [in]    topOfProcStack  Process Stack Pointer value to set
  113.  */
  114. static __INLINE void __set_PSP(uint32_t topOfProcStack)
  115. {
  116.   register uint32_t __regProcessStackPointer  __ASM("psp");
  117.   __regProcessStackPointer = topOfProcStack;
  118. }
  119.  
  120.  
  121. /** \brief  Get Main Stack Pointer
  122.     This function returns the current value of the Main Stack Pointer (MSP).
  123.     \return               MSP Register value
  124.  */
  125. static __INLINE uint32_t __get_MSP(void)
  126. {
  127.   register uint32_t __regMainStackPointer     __ASM("msp");
  128.   return(__regMainStackPointer);
  129. }
  130.  
  131.  
  132. /** \brief  Set Main Stack Pointer
  133.     This function assigns the given value to the Main Stack Pointer (MSP).
  134.     \param [in]    topOfMainStack  Main Stack Pointer value to set
  135.  */
  136. static __INLINE void __set_MSP(uint32_t topOfMainStack)
  137. {
  138.   register uint32_t __regMainStackPointer     __ASM("msp");
  139.   __regMainStackPointer = topOfMainStack;
  140. }
  141.  
  142.  
  143. /** \brief  Get Priority Mask
  144.     This function returns the current state of the priority mask bit from the Priority Mask Register.
  145.     \return               Priority Mask value
  146.  */
  147. static __INLINE uint32_t __get_PRIMASK(void)
  148. {
  149.   register uint32_t __regPriMask         __ASM("primask");
  150.   return(__regPriMask);
  151. }
  152.  
  153.  
  154. /** \brief  Set Priority Mask
  155.     This function assigns the given value to the Priority Mask Register.
  156.     \param [in]    priMask  Priority Mask
  157.  */
  158. static __INLINE void __set_PRIMASK(uint32_t priMask)
  159. {
  160.   register uint32_t __regPriMask         __ASM("primask");
  161.   __regPriMask = (priMask);
  162. }
  163.  
  164.  
  165. #if       (__CORTEX_M >= 0x03)
  166.  
  167. /** \brief  Enable FIQ
  168.     This function enables FIQ interrupts by clearing the F-bit in the CPSR.
  169.     Can only be executed in Privileged modes.
  170.  */
  171. #define __enable_fault_irq                __enable_fiq
  172.  
  173.  
  174. /** \brief  Disable FIQ
  175.     This function disables FIQ interrupts by setting the F-bit in the CPSR.
  176.     Can only be executed in Privileged modes.
  177.  */
  178. #define __disable_fault_irq               __disable_fiq
  179.  
  180.  
  181. /** \brief  Get Base Priority
  182.     This function returns the current value of the Base Priority register.
  183.     \return               Base Priority register value
  184.  */
  185. static __INLINE uint32_t  __get_BASEPRI(void)
  186. {
  187.   register uint32_t __regBasePri         __ASM("basepri");
  188.   return(__regBasePri);
  189. }
  190.  
  191.  
  192. /** \brief  Set Base Priority
  193.     This function assigns the given value to the Base Priority register.
  194.     \param [in]    basePri  Base Priority value to set
  195.  */
  196. static __INLINE void __set_BASEPRI(uint32_t basePri)
  197. {
  198.   register uint32_t __regBasePri         __ASM("basepri");
  199.   __regBasePri = (basePri & 0xff);
  200. }
  201.  
  202.  
  203. /** \brief  Get Fault Mask
  204.     This function returns the current value of the Fault Mask register.
  205.     \return               Fault Mask register value
  206.  */
  207. static __INLINE uint32_t __get_FAULTMASK(void)
  208. {
  209.   register uint32_t __regFaultMask       __ASM("faultmask");
  210.   return(__regFaultMask);
  211. }
  212.  
  213.  
  214. /** \brief  Set Fault Mask
  215.     This function assigns the given value to the Fault Mask register.
  216.     \param [in]    faultMask  Fault Mask value to set
  217.  */
  218. static __INLINE void __set_FAULTMASK(uint32_t faultMask)
  219. {
  220.   register uint32_t __regFaultMask       __ASM("faultmask");
  221.   __regFaultMask = (faultMask & (uint32_t)1);
  222. }
  223.  
  224. #endif /* (__CORTEX_M >= 0x03) */
  225.  
  226.  
  227. #if       (__CORTEX_M == 0x04)
  228.  
  229. /** \brief  Get FPSCR
  230.     This function returns the current value of the Floating Point Status/Control register.
  231.     \return               Floating Point Status/Control register value
  232.  */
  233. static __INLINE uint32_t __get_FPSCR(void)
  234. {
  235. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  236.   register uint32_t __regfpscr         __ASM("fpscr");
  237.   return(__regfpscr);
  238. #else
  239.    return(0);
  240. #endif
  241. }
  242.  
  243.  
  244. /** \brief  Set FPSCR
  245.     This function assigns the given value to the Floating Point Status/Control register.
  246.     \param [in]    fpscr  Floating Point Status/Control value to set
  247.  */
  248. static __INLINE void __set_FPSCR(uint32_t fpscr)
  249. {
  250. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  251.   register uint32_t __regfpscr         __ASM("fpscr");
  252.   __regfpscr = (fpscr);
  253. #endif
  254. }
  255.  
  256. #endif /* (__CORTEX_M == 0x04) */
  257.  
  258.  
  259. #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
  260. /* IAR iccarm specific functions */
  261.  
  262. #include <cmsis_iar.h>
  263.  
  264. #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
  265. /* GNU gcc specific functions */
  266.  
  267. /** \brief  Enable IRQ Interrupts
  268.   This function enables IRQ interrupts by clearing the I-bit in the CPSR.
  269.   Can only be executed in Privileged modes.
  270.  */
  271. __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
  272. {
  273.   __ASM volatile ("cpsie i");
  274. }
  275.  
  276.  
  277. /** \brief  Disable IRQ Interrupts
  278.   This function disables IRQ interrupts by setting the I-bit in the CPSR.
  279.   Can only be executed in Privileged modes.
  280.  */
  281. __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
  282. {
  283.   __ASM volatile ("cpsid i");
  284. }
  285.  
  286.  
  287. /** \brief  Get Control Register
  288.     This function returns the content of the Control Register.
  289.     \return               Control Register value
  290.  */
  291. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
  292. {
  293.   uint32_t result;
  294.  
  295.   __ASM volatile ("MRS %0, control" : "=r" (result) );
  296.   return(result);
  297. }
  298.  
  299.  
  300. /** \brief  Set Control Register
  301.     This function writes the given value to the Control Register.
  302.     \param [in]    control  Control Register value to set
  303.  */
  304. __attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
  305. {
  306.   __ASM volatile ("MSR control, %0" : : "r" (control) );
  307. }
  308.  
  309.  
  310. /** \brief  Get ISPR Register
  311.     This function returns the content of the ISPR Register.
  312.     \return               ISPR Register value
  313.  */
  314. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
  315. {
  316.   uint32_t result;
  317.  
  318.   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
  319.   return(result);
  320. }
  321.  
  322.  
  323. /** \brief  Get APSR Register
  324.     This function returns the content of the APSR Register.
  325.     \return               APSR Register value
  326.  */
  327. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
  328. {
  329.   uint32_t result;
  330.  
  331.   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
  332.   return(result);
  333. }
  334.  
  335.  
  336. /** \brief  Get xPSR Register
  337.     This function returns the content of the xPSR Register.
  338.     \return               xPSR Register value
  339.  */
  340. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
  341. {
  342.   uint32_t result;
  343.  
  344.   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
  345.   return(result);
  346. }
  347.  
  348.  
  349. /** \brief  Get Process Stack Pointer
  350.     This function returns the current value of the Process Stack Pointer (PSP).
  351.     \return               PSP Register value
  352.  */
  353. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
  354. {
  355.   register uint32_t result;
  356.  
  357.   __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
  358.   return(result);
  359. }
  360.  
  361.  
  362. /** \brief  Set Process Stack Pointer
  363.     This function assigns the given value to the Process Stack Pointer (PSP).
  364.     \param [in]    topOfProcStack  Process Stack Pointer value to set
  365.  */
  366. __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
  367. {
  368.   __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
  369. }
  370.  
  371.  
  372. /** \brief  Get Main Stack Pointer
  373.     This function returns the current value of the Main Stack Pointer (MSP).
  374.     \return               MSP Register value
  375.  */
  376. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
  377. {
  378.   register uint32_t result;
  379.  
  380.   __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
  381.   return(result);
  382. }
  383.  
  384.  
  385. /** \brief  Set Main Stack Pointer
  386.     This function assigns the given value to the Main Stack Pointer (MSP).
  387.     \param [in]    topOfMainStack  Main Stack Pointer value to set
  388.  */
  389. __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
  390. {
  391.   __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
  392. }
  393.  
  394.  
  395. /** \brief  Get Priority Mask
  396.     This function returns the current state of the priority mask bit from the Priority Mask Register.
  397.     \return               Priority Mask value
  398.  */
  399. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
  400. {
  401.   uint32_t result;
  402.  
  403.   __ASM volatile ("MRS %0, primask" : "=r" (result) );
  404.   return(result);
  405. }
  406.  
  407.  
  408. /** \brief  Set Priority Mask
  409.     This function assigns the given value to the Priority Mask Register.
  410.     \param [in]    priMask  Priority Mask
  411.  */
  412. __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
  413. {
  414.   __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
  415. }
  416.  
  417.  
  418. #if       (__CORTEX_M >= 0x03)
  419.  
  420. /** \brief  Enable FIQ
  421.     This function enables FIQ interrupts by clearing the F-bit in the CPSR.
  422.     Can only be executed in Privileged modes.
  423.  */
  424. __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
  425. {
  426.   __ASM volatile ("cpsie f");
  427. }
  428.  
  429.  
  430. /** \brief  Disable FIQ
  431.     This function disables FIQ interrupts by setting the F-bit in the CPSR.
  432.     Can only be executed in Privileged modes.
  433.  */
  434. __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
  435. {
  436.   __ASM volatile ("cpsid f");
  437. }
  438.  
  439.  
  440. /** \brief  Get Base Priority
  441.     This function returns the current value of the Base Priority register.
  442.     \return               Base Priority register value
  443.  */
  444. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
  445. {
  446.   uint32_t result;
  447.  
  448.   __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
  449.   return(result);
  450. }
  451.  
  452.  
  453. /** \brief  Set Base Priority
  454.     This function assigns the given value to the Base Priority register.
  455.     \param [in]    basePri  Base Priority value to set
  456.  */
  457. __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
  458. {
  459.   __ASM volatile ("MSR basepri, %0" : : "r" (value) );
  460. }
  461.  
  462.  
  463. /** \brief  Get Fault Mask
  464.     This function returns the current value of the Fault Mask register.
  465.     \return               Fault Mask register value
  466.  */
  467. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
  468. {
  469.   uint32_t result;
  470.  
  471.   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
  472.   return(result);
  473. }
  474.  
  475.  
  476. /** \brief  Set Fault Mask
  477.     This function assigns the given value to the Fault Mask register.
  478.     \param [in]    faultMask  Fault Mask value to set
  479.  */
  480. __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
  481. {
  482.   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
  483. }
  484.  
  485. #endif /* (__CORTEX_M >= 0x03) */
  486.  
  487.  
  488. #if       (__CORTEX_M == 0x04)
  489.  
  490. /** \brief  Get FPSCR
  491.     This function returns the current value of the Floating Point Status/Control register.
  492.     \return               Floating Point Status/Control register value
  493.  */
  494. __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
  495. {
  496. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  497.   uint32_t result;
  498.  
  499.   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
  500.   return(result);
  501. #else
  502.    return(0);
  503. #endif
  504. }
  505.  
  506.  
  507. /** \brief  Set FPSCR
  508.     This function assigns the given value to the Floating Point Status/Control register.
  509.     \param [in]    fpscr  Floating Point Status/Control value to set
  510.  */
  511. __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
  512. {
  513. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  514.   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
  515. #endif
  516. }
  517.  
  518. #endif /* (__CORTEX_M == 0x04) */
  519.  
  520.  
  521. #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
  522. /* TASKING carm specific functions */
  523.  
  524. /*
  525.  * The CMSIS functions have been implemented as intrinsics in the compiler.
  526.  * Please use "carm -?i" to get an up to date list of all instrinsics,
  527.  * Including the CMSIS ones.
  528.  */
  529.  
  530. #endif
  531.  
  532. /*@} end of CMSIS_Core_RegAccFunctions */
  533.  
  534.  
  535. #endif /* __CORE_CMFUNC_H */
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!