20141016_KUAS_Verilog_Divider_Mod3

/************************************/
/** 20141016 Mod 3 Divider         **/
/** Maker  : Yan                   **/
/** E-Mail : [email protected] **/
/** Date   : 2014/10/16 pm.10:30   **/
/************************************/

module Divider_Mod3(Clk, Clr, _output);
    input   Clk, Clr;
    output  _output;
    reg [1:0] cnt_p, cnt_n;
    reg clk_p, clk_n;

    assign  _output = clk_p | clk_n;
    always@(posedge Clk or posedge Clr)
    begin
        if(Clr == 1)
            cnt_p = 0;
        else
            if(cnt_p == 2)
                cnt_p = 0;
            else
                cnt_p = cnt_p + 1;
    end
    always@(posedge Clk or posedge Clr)
    begin
        if(Clr == 1)
            clk_p = 0;
        else
            if(cnt_p == 0)
                clk_p = 1;
            else
                clk_p = 0;
    end
    always@(negedge Clk or posedge Clr)
    begin
        if(Clr == 1)
            cnt_n = 0;
        else
            if(cnt_n == 2)
                cnt_n = 0;
            else
                cnt_n = cnt_n + 1;
    end
    always@(negedge Clk or posedge Clr)
    begin
        if(Clr == 1)
            clk_n = 0;
        else
            if(cnt_n == 0)
                clk_n = 1;
            else
                clk_n = 0;
    end
endmodule