VHDL - 7 Segment Display

--- Author: Matej Arlović, 2018.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bcd_segment is
    port(
        code: in std_logic_vector(3 downto 0);
        led: out std_logic_vector(6 downto 0)
    );
end bcd_segment;

architecture Behavioral of bcd_segment is
begin
    with code select
        led <=
            "0000001" when "0000",
            "1111001" when "0001",
            "0010010" when "0010",
            "0000110" when "0011",
            "1001100" when "0100",
            "0100100" when "0101",
            "0100000" when "0110",
            "0001111" when "0111",
            "0000000" when "1000",
            "0000100" when "1001",
            "0001000" when "1010",
            "1111110" when others;
end Behavioral;