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-- Company:
-- Engineer:
--
-- Create Date:   13:41:55 10/18/2017
-- Design Name:
-- Module Name:   C:/Users/mostafa.anwar/Desktop/ALU/ALU_test.vhd
-- Project Name:  ALU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY ALU_test IS
END ALU_test;

ARCHITECTURE behavior OF ALU_test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT ALU
    PORT(
         A : IN  std_logic_vector(3 downto 0);
         B : IN  std_logic_vector(3 downto 0);
         f1 : IN  std_logic;
         f0 : IN  std_logic;
         Y : OUT  std_logic_vector(4 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal A : std_logic_vector(3 downto 0) := (others => '0');
   signal B : std_logic_vector(3 downto 0) := (others => '0');
   signal f1 : std_logic := '0';
   signal f0 : std_logic := '0';

    --Outputs
   signal Y : std_logic_vector(4 downto 0);

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: ALU PORT MAP (
          A => A,
          B => B,
          f1 => f1,
          f0 => f0,
          Y => Y
        );

   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

  -- constant <clock>_period := 1ns;




   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100ms.
      wait for 10 ns;
        a<= "0110";
        b<= "1000";
        f0<='0';
        f1<='0';
         wait for 10 ns;
        a<= "0110";
        b<= "1000";
        f0<='1';
        f1<='0';
         wait for 10 ns;
        a<= "0110";
        b<= "1000";
        f0<='0';
        f1<='1';
         wait for 10 ns;
        a<= "0110";
        b<= "1000";
        f0<='1';
        f1<='1';

      -- insert stimulus here


   end process;

END;