Assignment-VHDL-3-Last

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-- Company:
-- Engineer:
--
-- Create Date:    23:26:17 02/27/2016
-- Design Name:
-- Module Name:    addAndSub - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_arith.ALL;
-- Uncomment the following library declaration if uSign
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity addAndSub is
    Port ( A,B : in  STD_LOGIC_VECTOR (3 downto 0);
            SignA : in  STD_LOGIC;
            SignB : in  STD_LOGIC;
            Operator : in STD_LOGIC;
            OutLEDSign : out std_logic_vector(2 downto 0);
            clk : in STD_LOGIC;
            seg : out STD_LOGIC_VECTOR(6 downto 0);
            com : out STD_LOGIC_VECTOR(2 downto 0);
            C : out  STD_LOGIC_VECTOR (4 downto 0));
end addAndSub;

architecture Behavioral of addAndSub is
    signal delay : integer := 0;
    signal countDelay : integer := 0;
    signal count : integer := 0;
    signal comtemp : std_logic_vector(2 downto 0) := "000";
    signal segtemp : std_logic_vector(6 downto 0) := "0000000";
    signal tempSignA : std_logic := '0';
    signal tempSignB : std_logic := '0';
    signal tempOperator : std_logic := '0';
begin

    process(clk, count)
        variable AInt, BInt, AB, digit, ten: integer;
    begin
            if clk'event and clk = '1' then
                -----------------------------
                if delay = 0 then
                    countDelay <= 0;

                    if SignA = '1' then
                        delay <= 1;
                        tempSignA <= NOT tempSignA;
                    end if ;

                    if SignB = '1' then
                        delay <= 1;
                        tempSignB <= NOT tempSignB;
                    end if ;

                    if Operator = '1' then
                        delay <= 1;
                        tempOperator <= NOT tempOperator;
                    end if ;

                else
                    countDelay <= countDelay + 1;

                    if countDelay = 5000000 then
                        delay <= 0;
                        countDelay <= 0;
                    end if ;
                end if ;


                -----------------------------
                AInt := conv_integer(A(3 downto 0));
                BInt := conv_integer(B(3 downto 0));

                if tempSignA = '1' then AInt := AInt*(-1);
                end if;

                if tempSignB = '1' then BInt := BInt*(-1);
                end if;

                if tempOperator = '1' then BInt := BInt*(-1);
                end if;

                OutLEDSign <= tempSignA&tempOperator&tempSignB;

                AB := AInt + BInt;
                C <= conv_std_logic_vector(AB, 5);

                count <= count+1;

                if count = 100000 then --digit
                    comtemp <= "110";

                    if AB < 0 then
                        AB := AB*(-1);
                    end if ;

                    if AB >= 30 then
                        digit := AB - 30;
                    elsif AB >= 20 then
                        digit := AB - 20;
                    elsif AB >= 10 then
                        digit := AB - 10;
                    else
                        digit := AB;
                    end if ;

                    if digit = 0 then
                        segtemp <= "0111111";
                    elsif digit = 1 then
                        segtemp <= "0000110";
                    elsif digit = 2 then
                        segtemp <= "1011011";
                    elsif digit = 3 then
                        segtemp <= "1001111";
                    elsif digit = 4 then
                        segtemp <= "1100110";
                    elsif digit = 5 then
                        segtemp <= "1101101";
                    elsif digit = 6 then
                        segtemp <= "1111101";
                    elsif digit = 7 then
                        segtemp <= "0000111";
                    elsif digit = 8 then
                        segtemp <= "1111111";
                    else
                        segtemp <= "1101111";
                    end if ;
                elsif count = 200000 then --ten
                    comtemp <= "101";

                    if AB < 0 then
                        AB := AB*(-1);
                    end if ;

                    if AB >= 30 then
                        digit := 3;
                    elsif AB >= 20 then
                        digit := 2;
                    elsif AB >= 10 then
                        digit := 1;
                    else
                        digit := 0;
                    end if ;

                    if digit = 0 then
                        segtemp <= "0111111";
                    elsif digit = 1 then
                        segtemp <= "0000110";
                    elsif digit = 2 then
                        segtemp <= "1011011";
                    elsif digit = 3 then
                        segtemp <= "1001111";
                    else
                        segtemp <= "0000000";
                    end if ;
                elsif count = 300000 then
                    comtemp <= "011";

                    if AB < 0 then
                        segtemp <= "1000000";
                    else
                        segtemp <= "0000000";
                    end if ;

                count <= 0;
                end if;

            end if;
    end process;
    com <= comtemp;
    seg <= segtemp;

end Behavioral;