-------------------------------------------------------------------------------
--
-- Title       : Fub2
-- Design      : szymik_krawczyk
-- Author      :
-- Company     :
--
-------------------------------------------------------------------------------
--
-- File        : C:\My_Designs\szymik_krawczyk\szymik_krawczyk\src\Fub2.vhd
-- Generated   : Mon Nov 26 10:32:58 2018
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {Fub2} architecture {Fub2}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;

entity Fub2 is
port(
    n           : in STD_LOGIC_VECTOR(3 downto 0);
    clk1m       : in STD_LOGIC;
    fout        : in STD_LOGIC;
    on_off      : in STD_LOGIC;
    Output1     : out STD_LOGIC;
    Output2     : out STD_LOGIC
    );

attribute LOC :string;
attribute LOC of clk1m :signal is "P17";
attribute LOC of fout :signal is "P39";
attribute LOC of Output1 :signal is "P40";
attribute LOC of Output2 :signal is "P41";

end Fub2;

--}} End of automatically maintained section

architecture Fub2 of Fub2 is
begin
    process(clk1m, n(0), n(1), n(2), n(3)) is
    variable start_stop     : std_logic := '0';
    variable licznik        : unsigned ( 3 downto 0) := "0000";
    variable dana           : unsigned ( 3 downto 0) := "0000";
    variable fr             : std_logic := '0';
    variable ff             : std_logic := '0';

    begin

        licznik(0) := n(0);
        licznik(1) := n(1);
        licznik(2) := n(2);
        licznik(3) := n(3);
        start_stop := on_off;

        if rising_edge(clk1m) then
            if fout = '0' and ff = '0' then
                fr := '0';
                ff := '1';
                dana := dana + "0001";
                if dana >= (licznik + "0001") then
                dana := "0000";
                end if;
                if dana < licznik then
                    Output1 <= '0';
                    Output2 <= '1';
                end if;
            elsif fout = '1' and fr = '0' then
                fr := '1';
                ff := '0';
                Output1 <= '1';
                Output2 <= '0';
            end if;
        end if;

    end process;

end Fub2;