-- this is the basic method to create a register with
-- data_d as its input, data_q as its output, and clk as the clock signal

process (clk, data_d, data_q)
begin
    if rising_edge(clk) then
        data_q <= data_d;
    else
        data_q <= data_q; -- included for clarity, the data is held constant
    endif;
end process;