zmigavac

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    20:22:45 11/29/2011
-- Design Name:
-- Module Name:    zmigavac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity zmigavac is
    Port ( iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           iLEFT : in  STD_LOGIC;
           iRIGHT : in  STD_LOGIC;
           iHAZ : in  STD_LOGIC;
           oLEFT : out  STD_LOGIC_VECTOR (2 downto 0);
           oRIGHT : out  STD_LOGIC_VECTOR (2 downto 0));
end zmigavac;

architecture Behavioral of zmigavac is
type tSTANJA is (sIDLE, sL1,sL2,sL3,sLR3,sR1,sR2,sR3);
signal sSTANJE,sSLEDECE_STANJE: tSTANJA;
signal sCNT: STD_LOGIC_VECTOR(15 downto 0);
signal sTC: STD_LOGIC;
begin


---brojac pola sekunde
    process (iCLK, inRST) begin
                if(inRST = '0')then
                    sCNT <= (others => '0');
                    elsif (iCLK'event and iCLK = '1')then
                        if(sCNT = x"B71B00") then
                        sCNT <= (others =>'0');
                        else sCNT <= sCNT+1;
                    end if;
                end if;
            end process;
        sTC<= '1' when (sCNT = x"B71B00") else '0'; ---izlaz komparatora je jedan kada brojac dodje na 0.5s

---opis automata

        ---1: kombinaciona mreza koja na osnovu trenutnog stanja i vrednosti ulaza generise kod narednog stanja
        process (iLEFT,iRIGHT,iHAZ, sTC, sSTANJE)begin

            case sSTANJE is


        when sIDLE =>
                case iLEFT is
                            when '0' =>sSLEDECE_STANJE<=sIDLE;
                            when '1' =>sSLEDECE_STANJE<=sL1;
                            when others => sSLEDECE_STANJE <=sL1;
                end case;

                case iRIGHT is
                             when '0' =>sSLEDECE_STANJE<=sIDLE;
                            when '1' =>sSLEDECE_STANJE<=sR1;
                            when others => sSLEDECE_STANJE <=sR1;
                end case;

                case iHAZ is
                            when '0' =>sSLEDECE_STANJE<=sIDLE;
                            when '1' =>sSLEDECE_STANJE<=sLR3;
                            when others => sSLEDECE_STANJE <=sLR3;
            end case;


        when sL1 =>
                case sTC is
                        when '0' =>sSLEDECE_STANJE <= sL1;
                        when '1' => sSLEDECE_STANJE<= sL2;
                        when others => sSLEDECE_STANJE <=sL2;
                end case;


        when sL2 =>
                    case sTC is
                        when '0' => sSLEDECE_STANJE <= sL2;
                        when '1' => sSLEDECE_STANJE<= sL3;
                        when others => sSLEDECE_STANJE <=sL3;
                    end case;

        when sL3 =>
                    case sTC is
                        when '0' => sSLEDECE_STANJE<= sL3;
                        when '1' => sSLEDECE_STANJE<= sIDLE;
                        when others => sSLEDECE_STANJE <=sIDLE;
                    end case;

        when sLR3 =>
                    case sTC is
                        when '0' => sSLEDECE_STANJE<= sLR3;
                        when '1' => sSLEDECE_STANJE<= sLR3;
                        when others => sSLEDECE_STANJE <=sLR3;
                    end case;

        when sR1 =>
                    case sTC is
                        when '0' => sSLEDECE_STANJE<= sR1;
                        when '1' =>sSLEDECE_STANJE<= sR2;
                        when others => sSLEDECE_STANJE <=sR2;
                    end case;

        when sR2 =>
                    case sTC is
                        when '0' => sSLEDECE_STANJE<= sR2;
                        when '1' =>sSLEDECE_STANJE<= sR3;
                        when others => sSLEDECE_STANJE <=sR3;
                    end case;

        when sR3 =>
                    case sTC is
                        when '0' =>sSLEDECE_STANJE<= sR3;
                        when '1' => sSLEDECE_STANJE<= sIDLE;
                        when others => sSLEDECE_STANJE <=sIDLE;
                    end case;

            end case;
    end process;


---2: kombinaciona mreza za opisivanje vrednosti izlaznog vektora na osnovu trenutnog stanja
---oLEFT : out  STD_LOGIC_VECTOR (2 downto 0)
---oRIGHT : out  STD_LOGIC_VECTOR (2 downto 0))

        process(sSTANJE)begin --izlaz zavisi samo od stanja
                case sSTANJE is
                    when sL1=>  oLEFT <= "001"; oRIGHT<="000";
                    when sL2=>  oLEFT <= "011"; oRIGHT<="000";
                    when sL3=> oLEFT <= "111"; oRIGHT<="000";

                    when sR1=> oRIGHT<= "001"; oLEFT<="000";
                    when sR2=> oRIGHT<= "011"; oLEFT<="000";
                    when sR3=> oRIGHT<= "111"; oLEFT<="000";

                    when sLR3=> oLEFT <= "111"; oRIGHT<="111";
                    when sIDLE=> oLEFT <= "000"; oRIGHT<="000";
                end case;
        end process;



---3:flip flopovi za smestanje koda trenutnog stanja, postavljanje pocetnog stanja
---je sinhrono sa signalom takta

    process(iCLK)begin
        if(iCLK'event and iCLK='1')then
            if(inRST='0')then
                sSTANJE <= sIDLE;
            else
                sSTANJE<=sSLEDECE_STANJE;
            end if;
        end if;
    end process;
end Behavioral;




----tb





--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:   22:25:27 11/29/2011
-- Design Name:
-- Module Name:   C:/Users/Branislav/Documents/University/Lprs/e13592/test_kodovi/ocena3/tb.vhd
-- Project Name:  ocena3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: zmigavac
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT zmigavac
    PORT(
         iCLK : IN  std_logic;
         inRST : IN  std_logic;
         iLEFT : IN  std_logic;
         iRIGHT : IN  std_logic;
         iHAZ : IN  std_logic;
         oLEFT : OUT  std_logic_vector(2 downto 0);
         oRIGHT : OUT  std_logic_vector(2 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal iCLK : std_logic := '0';
   signal inRST : std_logic := '0';
   signal iLEFT : std_logic := '0';
   signal iRIGHT : std_logic := '0';
   signal iHAZ : std_logic := '0';

    --Outputs
   signal oLEFT : std_logic_vector(2 downto 0);
   signal oRIGHT : std_logic_vector(2 downto 0);

   -- Clock period definitions
   constant iCLK_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: zmigavac PORT MAP (
          iCLK => iCLK,
          inRST => inRST,
          iLEFT => iLEFT,
          iRIGHT => iRIGHT,
          iHAZ => iHAZ,
          oLEFT => oLEFT,
          oRIGHT => oRIGHT
        );

   -- Clock process definitions
   iCLK_process :process
   begin
        iCLK <= '0';
        wait for iCLK_period/2;
        iCLK <= '1';
        wait for iCLK_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
inRST <= '1';
    iLEFT <= '1';
    iRIGHT<= '0';
    iHAZ<= '0';
    wait for iCLK_period*2;

    iLEFT <= '0';
    iRIGHT<= '1';
    iHAZ<= '0';
    wait for iCLK_period*2;

    iLEFT <= '0';
    iRIGHT<= '0';
    iHAZ<= '1';
    wait for iCLK_period*2;
inRST <= '0';
wait;

   end process;

END;